Книги2 / 1993 P._Lloyd,__C._C._McAndrew,__M._J._McLennan,__S._N

TABLE 1. Comparison of simulated and measured 3-sigma limits to specification limits

TABLE 2. Predicted and measured (in parentheses) correlations

5.3Device Correlations with In-lines and Process Controls

Correlations between device characteristics and in-line measurements were computed for poly linewidth clitical dimension (poly CD), Tox, and sheet resistances. While poly CD and Tox are measured in-line, the sheet resistance is not. Using pilot wafers, the sheet resistance measurements could have been made in-line on a batch basis.

The predicted and measured correlations were compared. There is good agreement between measured and simulated correlations. Due to limitations in the CIM database, it was not possible to compute the Tox measured correlations. Note that the linewidth variations dominate both ldp and ldn while neither Vtp or Vtn are strongly correlated with poly linewidth variation. It is the common dependence on linewidth variation that creates the correlation between ldn and ldp.

5.4Applications to Process Control

The results in the previolls section demonstrate that pdFab can predict the device parameter distributions observed at wafer electrical test. This prediction is based on process con-

trol variations. Hence, pdFab is providing the service of virtual factory by mimicing not only the ideal hehavior hut also the manufacturing variation that will certainly occur during production. This service is the needed component for the design of process control strategies.

TABLE 3. Predicted and measured (in parentheses) correlations between device parameters and in-line measurements

Process control strategies are designed to assure that devices meet specifications at wafer electrical test inspite of the process variations. Typically, in-line measurements are measured and specification Imits are established to assure that the devices will meet specification limits at electtical tests. Picking the correct in-lines to measure and design specification limits for those in-lines is difficult since it has not been possible to determine the correlations hetween parameters aprior to manufactUling many lots.

Since pdFab can be used to determine the con'elations between parameters, it is now possible to detelmine process control strategies based on modeling. The first step in process control design is determining if the in-line measurements provide enough observability to determine device variations. With the cOlTe1ation data presented in the previous section, its possible to detelmine if the in-line measurements are sufficient.

The CMOS process flow specifies that gate oxide thickness and poly CD are to be monitored dUling production. The goal is to assure that the device meets the desired specifications. Since the poly CD and Tox are uncorrelated, we can compute the percentage of the variance of the four monitored device characteristics (Vtn, Vtp, Idn, and Idp) that can be predicted via in-line measurements hy summing the percentages for each individual measurement. The results are summmized in Table 4.

After the gate oxidation in-line is measured, a large percentage of the variance of Vtn has been determined. Hence, this in-line can be used to control Vtn. The poly CD measurement only accounts for 58% of Idn, but if this information were used along with the Tox in-line, 85% of the Idn variation could be predicted once the poly CD is measured.

The observahility for the PMOS transistor is not as good. Only 59% of the Idp variation and 0.4% of the Vtp variation can be observed from measUling the two in-lines. This is because a large amount of the PMOS transistor's variation is controlled by variations in the buried channel dopant concentration. We determined this by examining the correlation of Vtp and Idp with the N-well sheet resistance Rsh). Since we cannot get an in-line measurement of the N-well Rsh after gate oxidation, it is not possible to monitor Vtp and Idp

using in-line measuremenL~. The only way to guarantee that these two device charactel1stics are within the specifications limits is to explicitly measure them at electrical test. Hence quality assurance can only be achieved via direct testing. The conclusion of this analysis is that while close-looped control can be used to improve the NMOS transistor, the PMOS transistor can only be manufactured via open-loop control.

TABLE 4. Percentage of the device variance predicted by in-line measurements

5.5Application to Worst Case Circuit Models

Typically, worst case models are released to circuit designers which represent the comers of the process where circuits are likely to fall out of specification. For the National process, each transistor is released with two worst case models, weak and strong. The weak transistor has both a high threshold voltage and low drive current while the strong transistor has high drive current and low threshold voltage. The NMOS and PMOS models are treated as being independent (i.e, it is necessary to simulate the weak-strong condition).

By examining the predicted con·elations, we see that the NMOS and PMOS transistors are significantly related. Hence the strong-weak case is unlikely, as shown in Figure 18. From the distribution we picked points to represent realistic worst case corners. For example the comer which has the strongest NMOS transistor also had the strongest PMOS transistor. The selected worst case drive CUlTent comers are marked with circles in Figure 18.

Typically, it is assumed that the maximum dlive current transistor also has a low threshold voltage while the minimum drive transistor has a high threshold voltage. The implied assumption is that the correlation between Vt and Id is 1.0. As shown in Figure 19, this is not the case. On the scatterplot we have drawn a line. If the assumption were correct, all data points would have to lie on this line. In Figure 19, we have circled two cases were the transistor has typical threshold voltage, but the drive currents are close to opposite ends of the distribution. We generated BSIM models at the corners circled.

6.Conclusions

Our expetience with PREDITOR and pdFab has demonstrated that technology CAD tools hold wide promise in manufactming, and providing the link between design and manufacturing. The experimental results show that the distribution of device charactetistics and their con·elations can be accurately predicted. The statistical data can be used to determine the adequacy of in-line measurements for process control, and to generate a realistic set of worst-case device parameters.

It has been estimated that a $3B market in technology CAD tools could be supported if their use increased manufactm1ng yields by 10% [14]. In this paper we have shown that when assembled into the appropriate framework, such promise has a realistic chance of being fulfilled. The essential elements of this framework are a flexible wafer representa-

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Edited by F. Fasching, S. Halama, S. Se1berherr - September 1993

Technology CAD at Stanford University:

Physics, Algorithms, Software, and

Applications

R.W. Dutton and R.J.G. Goossens

Center for Integrated Systems, Stanford University, Stanford, CA 94305, USA

1.Introduction

The evolution of technology computer-aided design (TCAD) over the past two decades has been remarkable. During this period we have wittnessed the ubiquitos use of circuit simulation for IC design, the broad acceptance and use of device analysis for technology design and the innovation of new classes of simlators for process and equipment modeling. Much of this expanded role for TCAD has been driven by the IC revolution itself where device dimensions have been reduced by more than 20 fold and gate densities per chip have increased by more than 10,000 times. The growing need for and role of TCAD is mandated by requirements on control over the manufacturing process, electrical reliability, as well as business aspects like minimizing the time to market. Moreover, the design issues of both high-speed and low power -- each from a very different perspective -- require greater care and precision in IC design.

The purpose of this paper is to provide an overview of the TCAD efforts at Stanford. Over the past two decades the efforts have broadened from research in individual tools (i.e. SUPREM and PISCES) and their physical models towards integrated software systems and applications. Here we will provide a discussion based on the latter rather than fonner point of view. In Section II we use specific problems to illustrate progress in both tool development and applicability to practical IC design problems. This includes key issues related to consortia-based collaborations and the growing need for infrastructure to support both TCAD software as well as graphics and other interfaces. Section ill turns to recent advances in physical models with emphasis on calibration strategies. The discussion of algorithms and the role of parallel computation is presented in SectionN. Finally we give a summary of highlights presented in this paper.

2.Application-Driven TCAD

2.1Aladdin-CAD

As suggested in the Introduction, TCAD is driven by a need to accuratelyand quickly predict factors that improve perfonnance, reliability and yield for IC technologies. Over the past two years we have been involved in a collaborative project with several industrial partners and funded by the State of California's Department of Commerce. The Aladdin-CAD Project (Analysis ofadvanced devices based on industry-networked CAD) has focused on interesting device and technology innovations as well as improvements related to tool usability and robustness. The following examples demonstrate progress in this applicationdriven approach.

114 R.W. Dutton et al. : Technology CAD at Stanford University

High-density silicon devices

Random Access Memory (RAM) and especially Static or SRAM have been a key pacing factor in microprocessor system performance. The trade-offs involved in increasing density and speed while achieving high yields has been a major challenge to the industry. During the course of the Aladdin-CAD project we have worked closely with Cypress Semiconductor in the modeling and simulation oftheir next-generation SRAM technology. While the details of their technology and devices are proprietary, the following inverter example gives a clear indication of the issues both in and user interfaces.

Figure I 3D Solid Model of an inverter structure generated with a Stanford developed geometric-modeling tool, based on ACIS [1] for the solid model and AVS [4] for visualization.

Figure 1 shows a 3D solid model of a CMOS inverter, half of a simple SRAM cell that has been created using a Stanford-developed tool based on a commercial geometry-modeling library, ACIS from Spatial Technologies [1]. This result clearly demonstrates to us the important role played by the underlying information models. Specifically, the structure's layout was defined using the Cadence layout system and the standardized CIF format was used to provide a set of surface polygons, which the ACIS-based tool used to create the solid geometry model. From this geometric model, two consistent alternative data representations were created, namely one conforming to the HDF-Vset standard [2] to interface with visualization and the other to the SWR 3D prototype based on the present standard [3] to support gridding for device analysis. Figure 1 was created using AVS [4], an advanced graphically programmable environment for the manipulation and visualization of scientific data. It was in fact through such visualization and exploration of many of the complex fea-

tures of the SRAM structure that our collaborators at Cypress were able to understand and unravel design rule trade-offs and potential problems that could have affected yield.

Figure 2 Inverter cross section. Grid was created using 5MB.

Figure 2 shows a stylized cross-sectional view of one of the inverter pair shown above and the analysis grid created automatically by 5MB. This is a gridding tool that is based on Meshbuild from ETH, Zurich [6] and has been enhanced by Stanford [5]. Using this gridded structure we could analyze several features of the cell performance using PISCES-

MP [7]] or other device analysis programs. Specifically, the cell switching properties as well as the latchup immunity have been studied using different stimulus and boundary conditions, including circuit elements for mixed-mode analysis. Such large structures require very large grids and hence can only be supported by the computational resources offered by large-scale parallel systems. In Section IV we will discuss some of the issues involved in using parallel computation with multi-processors, based on our experience with a multi- processor-version of PISCES. It is evident however that the ability to use in excess of 100,000 grid points in a 2D device simulator is an essential ingredient in the accurate analysis of multi-devices cross section that are extracted from standard cells.

High-voltage silicon devices

There exists a variety of special-purpose devices that essentially require simulation and modeling as part of the design process. High voltage device design is one such class and Stanford has made a number of contributions to this field [8]. Again in the context of the Aladdin-CAD project, we have worked closely with an industrial partner, National Semiconductor, to help in the design of a next generation high-voltage bipolar process. The focus of this design effort was to assess for this new process technology the sensitivity of critical device-performance parameters with repect to critical dimensions and in particular to assymmetry due to mask misalignment. In particular, a key issue with high-voltage devices is to correctly predict breakdown characteristics. This is difficult owing to not only unique physical effects but also numerical challenges to correctly control the boundary conditions throughout the tracing of the I-V curves.