Книги2 / 1993 P._Lloyd,__C._C._McAndrew,__M._J._McLennan,__S._N

FIGURE 8. Simplified Tel script for threshold voltage extraction

#= Calculates the threshold voltage for MOS transistors by finding the x-intercept #= of the regression line through a user-specified region of the Vgs x Id curve.

#= Parameters:

#= Vds, Vbs, Vgs_Iow, Vgs_high, num_points

#= Outputs:

#= /iv/$dev_name/Is_NMOS -- 0 if NMOS, -I if PMOS, /iv/$dev_nameNth -- threshold voltage

set dev_name $PDFAB_Device

# Is this an NMOS? Set to 0 if NMOS -I if PMOS set Is_NMOS [slling first "NMOS" $dev_name]

seCdefault Vds 0.5 seCdefault Vbs 0.0 seCdefault Vgs_low 0.0 set_default Vgs_high 2.5 seCdefault num_points 2

#Change signs if it's a PMOS

if ($Is_NMOS == -I) ( set Vds [expr -$Vds]

set Vbs [expr -$Vbs]

set Vgs_low [expr -$Vgs_low] set Vgs_high [expr -SVgs_high]

)

source [info library]Nlh.tcl

source [info library]/Iea.<;l-squares.tcl

GAereate /iv List I

GAcreate /iv/$dev_nrune List I

GAset /iv/$dev_name/num_points/ Snum_points

# begin algorithm

set Vs [expr O.O-$Vbs]

set Vgs_step [expr ($Vgs_high-$V gs_low)/($num_points-1.0)] for (set i O) ($i < $num_points) (incr i) {

set Vgs [expr $VgS_low+$i*$Vgs_step] lappend Vgs_list SVgs

set currents [2D_solve $dev_nrune \

[expr $Vgs+$Vs] $Vs [expr $VdH$VS] 0.0] set Id [lindex $cUlTents 0]

lappend Id_Iist $Id

}

set regression [Is_regress $Vgs_list $Id_Iist $num_points] set m [Iindex $regression 0]

set b [lindex $regression 1] GAcreate /iv/$dev nameNUl Double

GAset /iv/Sdev_nameNU1/ [expr -$b/$m]

4.1Statistical Simulation: Monte Carlo

PdFab supports a number of task-level simulation modes, including Monte Carlo (both standard MC and latin hypercubes), sensitivity simulation, fractional factorials, and lot splits. We explain in detail the justification for Monte Carlo simulations since they are critical for variation prediction.

Our goal in this work is to use process and device simulation to determine the distribution of device characteristics (e.g., Idmax, and Vt) based on the distributions of in-line measurements and process controls. Since the functional relationship between process controls and devices characteristics is not well understood, it is not possible to simply transform the

FIGURE n. Doping concentrations in a vertical NPN BJT

FIGURE 12. Flow chart for Monte Carlo simulation

4.2Data Translation

At the completion of the Monte Carlo simulation, distributions of device characteristics, their inter-correlations, and their correlations with in-lines and process controls can be

plotted. To achieve reasonable confidence in the predicted con·elations, the number of runs must be fairly large (typically 50-200).

The advantages of using Monte Carlo simulation to compute correlations and standard deviations are:

• A large sample can be generated in a short amount of time

A Monte Carlo simulation with a sample size of 100 can be generated in 4 to 30 hours of simulation time, yet it represents the production of 100 lots.

• A single process flow is used

In a pilot line, process control skews corrupt the electrical test database since they represent changes which do not happen during normal manufacturing.

•In-line, electrical tests, and actual process control settings are all collected in a single database

Many times, in-line measurements are stored in a CIM database while electrical tests are stored in a second database. Combining and cross-correlating this information is difficult. Moreover, during Monte Carlo simulation we know the actual process control setting for each run. Hence it is possible to detennine the con·elation between an individual control and device characteristics. However, the velY nature of process control variation is that it cannot be measured. With measured data it is not possible to be able to determine the correlation between the variations of an implant and device characteristics.

4.3Wafer-Level Simulation

New processes rely on single wafer processing and large diameter wafers to achieve run- to-run unifOlmity at affordable costs. As a result, increased emphasis has been placed on equipment modeling for predicting within-wafer uniformity. Presently there is no commercial system available that can simulate equipment models in the process flow, or predict wafer maps of transistor charactelistics given the spatial dependencies of process controls. By making use of CDB's global attlibutes, both the wafer map (centimeter-scale) as well as the detailed device structure (micron-scale).

In-line infonnation from equipment models is used in wafer-level TCAD simulations to predict the eventual distribution of device characteristics, as shown in Figure 13. Thus, process control can be used to determine whether the equipment is performing to the desired level of quality (equipment control) and whether the product in production will likely meet specification (product control). pdFab has already been used to determine process control limits for in-line measurements to assure that device specifications are met [11]. By extending pdFab to handle equipment models, it will be possible to use it for the control of unit process steps.

With the addition of equipment modeling and wafer simulation, users will be able to simulate process integration. As demonstrated in the MMST project [23], changes in equipment settings will result in different uniformity characteristics. By including equipment models in the simulation of the process flow, the effect of equipment changes on the unifonnity of transistor charactelistics can be quantified.

As an example, consider the following experiment perfOlmed with pdFab. The experiment assumes that gate oxidation temperature, photoresist thickness, and implantation dose are spatially dependent. In most process simulators, process controls are considered to be con-

sure sequences are reused to minimize total simulation time. Two-dimensional process simulation is supported using SUPREM-IV [15]. pdFab supports both the TMA and Silvaco versions of SUPREM-III and SUPREM-IY.

Topography simulation is an essential part of the integrated process simulation system. A number of tasks ranging from process integration to layout design role development require accurate predictive simulation of topography changes caused by steps such as deposition, lithography and etching. A complete lithography simulation program called METROPOLE [18] has been developed at CMU and will be integrated into the next generation of the framework. METROPOLE implements a true vector 2-D model, based on efficient solution of Maxwell's equations by the waveguide method. METROPOLE is capable of simulating photoresist deposition, bleaching, post-baking and development for dimensions below O.5um. It can model the stepper optics, non-planarity of lithographic mask (especially important for phase-shifting masks) and arbitrary nonplanarities of the substrate wafer. This program has been verified extensively for a number of tasks such as alignment modeling, defect simulation and technology feasibility studies. Since it takes as inputs arbitrary layer stacks with the detailed description of shapes and produces as output the realistic window in the photoresist layer, it is ideally suited for use in PREDITOR and pdFab.

Although, as we described earlier, the focus of PREDITOR and pdFab is the simulation of devices within one chip, due to the CDB global attributes it is possible to enter, for example, the spatial distribution of the simulation parameters within a wafer or even from wafer to wafer. This permits extending process simulation to include equipment model which operate on a centimeter scale. For example, it is possible to predict nonuniforimty in the thickness of an LPCVD polysilicon layer by modeling the deposition rate distribution as a function of process recipe parameters and spatial coordinates on a given wafer. A comprehensive equipment simulation system which utilizes the FLUENT computational fluid dynamics program [9] has been developed which permits accurate simulation of the physics and chemistry of industrial deposition systems. To date it has been applied to problems such as PECVD of silicon nitride and CVD of tungsten. Such accurate physical models are then used to generate simplified, but still physically-based, analytical models using PHENOM [7][30]. These PHENOM-generated equipment models are then automatically included in the library of process models. Models described in C require relinking of the libraries. Models described in TcI can be used immediately. An equipment model for LPCVD of polysilicon has been included in the library.

4.6Device Simulation

In order to map from device structures to device parameters, transistor I-V characterisitics must be computed via device simulation. The simulation clients supported by pdFab include SIMOS, a 2-D numerical solver for MOS [26]; BISIM, a 2-D solver for BJT's [27], and a compact analytical solver for BJT SPICE model cards. TMA Medici and PISCES are also supported. All of these simulators take the doping field from the virtual grid as input data.

4.7Parameter Extraction

Device I-V characteristics are translated into compact circuit simulation models via parameter extraction. In PREDITOR, a simple SPICE level 2 model extractor was provided. In pdFab, extraction scripts are specified via the Tcl-based extension language. An

example of such a sClipt is shown in Figure 8. The extraction programs are separate from the device simulation controls and meshing. Hence, they can be re-used for many devices and simulators without changing them. They can be stored in a pdFab library so others can use them. Standard sClipts are provided, such as Vt, VAF, and BSIM model extraction. PdFab has physically-based SPICE model extraction for statistical analysis. These routines support industry-standard SPICE models such as BSIM, but make use of deterministic physical extraction. This method is described in more detail in the next section.

4.7.1SPICE Model Extraction

In order to provide meaningful statistical infonnation, the BSIM model parameters must be extracted in a physically-based manner. Parameter optimization, as shown in Figure 15, can result in a non-unique parameter set. This adds valiance to the parameter distlibutions. Hence optimization-based methods cannot be used for statistical analysis. The pdFab parameter extraction methodology incorporates both two-dimensional dopant layout information and efflcient two-dimensional numeJical device simulation performed using SIMOS or Medici.

FIGURE 15. Flow chm·t of conventional optimization based device chal'actel·i7.ation pl'Ocedure

- must fab beforehand

- values have no physical grounding

- fit is good for only one transistor

Optimizer

Several BSIM model parameters have physical definitions and can be determined directly from the dopant profile. Among these model parameters are the channel length and width, gate oxide thickness, drain and source resistance, and the capacitance parameters For short channel devices, the threshold voltage is strongly effected by the drain and source depletion regions. Thus, two-dimensional numerical device simulation is required to accurately extract the threshold voltage model parameters. Although the difference in the Fermi potential between the monosilicon channel and polysilicon gate can be physically extracted from the dopant profile, the other threshold model parameters are determined via 2-D device simulations. Similarly, parameters for the average channel mobility, gate field mobility reduction factor, the I-V relationship in the linear and saturation operating regions, and subthreshold drain current are each extracted in tum using a total of 20 2-D device simulations. This model parameter extraction approach does not make use of any special 2-D device simulator features, and so it can be implemented with any of the device simulators within pdPab.

5.Experimental Results

PdFab has been applied to the analysis of BIT, CMOS and BiCMOS processes. Instead of supporting a single approach to manufacturability analysis, pdFab is used as a tool to support many different strategies. In this section we show the results of using pdFab to determine the manufacturability of a National Semiconductor CMOS process, using a Monte Carlo simulation approach to predict correlations and vaIiances of device characteIistics. The process was a 0.8um CMOS process with LDD NMOS and LDDlbuIied channel PMOS devices. The goals of the analysis were to determine whether the process could be controlled, and to compute realistic worst case limits for device SPICE models.

The process was entered into pdFab and simulated with SUPREM-Ill as the process simulator. The analytical doping profiles were calibrated to the SUPREM profiles by adjusting the diffusivity of boron, arsenic and phosphorus, and the segregation coefficient of boron and phosphorus. By doing so, the analytical profile models could be used duIing the Monte Carlo simulation. The lateral diffusivity of boron and phosphorus were adjusted to achieve the correct effective channel length. PdFab's ability to incorporate a spectrum of models was cIitical for this activity. Given the number of Monte Carlo runs made (and the sample size for each), it would have been prohibitively time consuming to perfonn all simulations using SUPREM-Ill.

Standard deviations were then assigned to key process controls based on specification limits. For implantations, the standard deviation of the dose and energy was set to 5% of the process control setting. Initially, the standard deviations of furnace temperatures and poly linewidrh were set to match specification limits of the oxide thickness and cIitical dimension. On inspection of CIM data from a pilot line, it was found that actual deviations differed from the specification limits. In subsequent experiments the standard deviations of furnace temperature and poly linewidth were set to match measured data. The standard deviation of the furnace temperature was set to two degrees for high temperature steps. Using a two-degree standard deviation, the simulated standard deviation of gate oxide thickness was close to measurements. The poly linewidth standard deviation was set to O.039um.

5.1I-V Prediction and SPICE Models

Once entered, the process was simulated with all control settings at their designed values. PdFab generated BSIM models (HSPICE level 13 model) for both the NMOS and PMOS transistors. The I-Vs generated with the BSIM model were compared to curves measured from "typical" transistors in Figures 16 and 17. Since we do not know the exact conditions that were used to fabricate the typical transistor, the purpose of comparing these curves is not to detelmine a goodness of fit measure. Rather, we demonstrate that the simulated I-Vs are similar to the typical measured transistor. The BSIM model was extracted by using results from the SIMOS device simulator. The extraction computation (including the process and device simulation) takes 15 CPU-minutes on an IBM RS60001550.

5.2Statistical Data

With satisfactory results from the simulation of the designed process, a Monte Carlo simulation of 100 samples was run. Rather than doing a full BSIM extraction for every point, the threshold voltage and Id Max (5X5 current) were simulated at every point for both NMOS and PMOS transistors. The Monte Carlo simulation with 100 process steps required 8 hours of CPU time on the IBM RS60001550. The simulated distIibutions of

device parameters were compared with the specification limits and distributions of measured data. In this process, the specification for each device parameter represent the mean value, +3 sigma and -3 sigma points on the distribution. In Table 1 the percentage difference between the predicted 3-sigma limits, the specification limits, and the measured 3- sigma limits are presented. The measured data consisted of approximately 1000 sample points per parameter colIected from during fiscal year 1993. From the table, it is clear that there is good agreement between the predicted distributions and both the measured distribution and specification limits. There is slightly better agreement with the measured distribution than the specification limit.

FIGURE 16. NMOS I-V curves - measul'ed and BSIM

Vds

FIGURE 17. PMOS I-V CUl'ves - measUJ'ed and BSIM

Vds

Also computed are the correlations between Vt and Id were also computed, as shown in Table 2. Given the sample size, all correlations, with the exception of the correlation between Vtn and Idp, are within the statistical confidence limit of the measured values. It is interesting to note that the correlation between devices (Idn and Idp) is greater than the correlation within the devices (ld vs. Vt). This infonnation is used when generating worst case corners for design.