Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

channel, drain/source, and field regions of each type of device. The decision to use an n-well approach was based largely on the compatibility with the existing nMOS process. The starting material is p-type, < 100 > oriented silicon with a doping concentration of ~ 9 x 1014 cm-3. The n-well is implanted with a p 31 dose of 2.5 x 1012 cm-2 at an energy of 100 KeV. The n-well is then annealed, oxidized for 32 minutes at 1000 °C, and then driven-in for 960 minutes at 1150°C in an inert ambient. The surface concentration of the n-well (~ 1 X 1016 cm-3) is determined primarily by the need to maintain a sufficiently high surface concentration to prevent field inversion of the n-well. The depth of the n-well (~ 4 {tm) is then determined by the need to prevent punch-through of the parasitic vertical pnp transistor under worst case bias conditions.

After the n-well drive-in oxide is removed, a thin (~ 400A.) layer of "pad" oxide is grown in dry ambient for 48 minutes at 1000°C. Low Pressure Chemical Vapor Deposition (LPCVD) SbN4 is deposited to complete the mask for the locally oxidized field regions. Schematic pictures are shown in Figure 2.1 (a), Chapter 2. After patterning the active regions in the Si3N4 (and while the active-region photoresist is still in place) a second layer of photoresist is patterned which is used to protect the n-well regions from the n-channel field implant. After the Bll implant of 1 x 1013 cm-2 at 100 KeV, the thick field oxide is grown in a pyrogenic steam ambient (partial pressure of H2 0 ~ 0.80 atmospheres) for 190 minutes at 1000°C. The initial thickness of this field region is ~ 7500A., but is later reduced to ~ 6000A. by various unmasked Si02 etches prior to polysilicon deposition.

For a gate thickness of 400A., it is impractical to use a single implant to shift the threshold of both the n- and p-channel devices. Therefore a blanket (i.e. unmasked) Bll implant of 4 x 1011 cm-2 at 35 KeV is used to shift the threshold of the p-channel devices (and the n-channel devices as well) to the desired level VTp ~ -l.OV. This is followed by an additional masking step which protects the p-channel devices while the n-channel devices receive an additional Bll implant of 3.5 x 1011 cm-2 at 35 KeV to bring their threshold up to a designed value of VTn ~ 0.85V. These threshold voltages have been selected to insure adequate protection from sub-threshold leakage currents. The p-channel device with an n+ polysilicon gate electrode becomes a buried-channel device if we try to shift its threshold to a symmetrical value of VTp ~ -0.85V. Buried channel devices typically

28 CHAPTER 1. TECHNOLOGY-ORIENTED CAD

exhibit drain-induced barrier lowering and possess inferior sub-threshold characteristics. This point is discussed further in Chapter 5. Because neither the n-channel nor the p-channel device is operated with "substrate" potentials other than OV and VDD, respectively, an additional deep implant to prevent drain/source punch-through problems was not used. In order to avoid potential damage of the gate oxide due to either the implants and/or resist processing, the threshold-shifting implants were made through a sacrificial 400A oxide. Once this gate oxide is removed, the actual gate oxide is re-grown in a dry O2 ambient for 48 minutes at 1000°C. Redistribution and segregation of the boron during the gate oxidation must be carefully considered in order to achieve good threshold control during this step.

The LPCVD polysilicon is deposited at 620°C, doped using POCb (1100 ppm partial pressure at 950°C for 30 minutes), and dry etched in a plasma reactor using a mixture of SF6 and C2CIF5. A photoresist layer defining the n+ source/drain and n-well contact regions is applied and a high dose (6 x 1015 cm-2 at 100 KeV) arsenic implant is performed followed by an annealing for 20 minutes at 950°C. The p+ regions are then defined with a photoresist layer and the wafers are implanted with Bl1(1 x 1015 cm-2 at 35 KeV) followed by a lower temperature annealing/oxidation of 57 minutes at 850°C (27 minutes in a N2 ambient and 30 minutes in an O2 ambient). This oxidation prevents the penetration of unwanted phosphorus into the p-channel source/drain regions from the phosphorus-glass which is subsequently deposited in a low temperature oxide reactor at 450°C. After phosphorus-glass deposition, the wafers are placed in a pyrogenic steam ambient for 30 minutes at 900°C to more fully activate the p-channel source-drain regions and to densify the phosphorus-glass. Even in a steam ambient there is little, if any, reflow of the phosphorus-glass layer. Sputtered aluminum alloy deposition is used to provide good step coverage in the process.

Following the densification step the contact holes are patterned with photoresist and etched using a plasma process. Because the source/drain junctions are quite shallow and the selectivity of the plasma etch is about 3 : 1 (Si02 :Si), the use of end-point detection at this step is particularly important in order to insure contacting of shallow junctions during subsequent metallization procedures.

Following the contact hole etch, a thin (:::::: lOOOA) layer of tungsten is deposited in a low pressure chemical vapor deposition reactor and then a sputtered 1.0 pm layer of aluminum alloy is used for the final

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DEPTH FROM SURFACE (microns)

Figure 1.14: Semi-logarithmic plot of concentration versus depth for the implanted boron profile (7.5 x 1011 cm-2 ) in the n-channel device (cross-section 2 in Figure 1.12). The solid line shows SUPREM results and the dashed line gives spreading resistance measured data.

metallization layer.

The structures and impurity distributions resulting from SUPREM III simulations at each cross-section indicated in Figure 1.12 are shown in Figure 1.14 through Figure 1.17. The corresponding measured concentration profiles derived from spreading resistance measurements are overlaid in each of these figures. In each case only the net, electrically active part of the profiles are plotted.

Figures 1.14 and 1.15 show the impurity distributions for crosssections 2 and 1, the n- and p-channel gate regions, respectively. In each case we see the thick phosphorus-glass covering the polysilicon gate. Next the thin 400A gate oxide layer is observed followed by the bulk silicon with respective n-channel (Figure 1.14) and p-channel (Figure 1.15) implants. For the n-channel device the structure has a p-substrate with the added boron implant to create the doping peak near the surface. In the case of the p-channel device, the well is n-type and the unmasked boron implant compensates the well doping, thus giving the apparent doping dip at the surface. The agreement in both cases between simulation and measurement is quite good. The desired threshold voltage for each of these devices was VTp = -1.0V and VTn =O.85V.

DEPTH FROM SURFACE (microns)

Figure 1.15: Semi-logarithmic plot of concentration versus depth for the n-well and implanted boron counterdoping profile (4 x 1011 cm-2 ) in the p-channel device (cross-section 1 in Figure 1.12). The solid line shows SUPREM results and the dashed line gives spreading resistance measured data.

Further details of electrical properties of these two devices will be discussed in subsequent chapters. Figures 1.16 and 1.17 show the sourcedrain diffusions for the p-channel and n-channel devices, respectively.

For the n-channel arsenic diffusions the junction depth is about 0.27 j.Lm whereas the boron junctions are at about 0.4 j.Lm. Note the differences both in background doping and peak surface concentrations between the two profiles. In the arsenic case the peak is greater than 1020 cm-3 and the substrate shows the nonuniform doping effect due to the threshold adjusting boron implant. Although the simulated and measured values differ by about a factor of two near the peak, this error is expected because of the limited resolution of the spreading resistance technique. For the boron profile the peak is less than 1020 cm-3 and the bulk is dominated by the uniform phosphorus well concentration.

The fabrication steps used in the Stanford process have been presented so far. Although the reader may not be able to fully appreciate the implications of each step at this time, in later chapters we will return to study many of them in greater detail.

The above discussion may seem rather involved and complicated for those studying device technology for the first time. The primary reason for this detailed presentation is to serve as a reference for material discussed in subsequent chapters. Namely, we will consider various aspects of MOS and bipolar devices in the remainder of the text. When needing suitable technology representations, wherever possible we will return to this section to collect the representative information.

1.6Summary

This chapter presents a broad-brush picture of both technology evolution beginning with the bipolar transistor and evolving to some recent trends in CMOS technology. The motivation for Technology CAD is outlined with a few typical examples used to illustrate the points. This book takes a rather unconventional approach in that the availability of the CAD tools used in this work make it possible for the reader to have a hands-on experimentation phase. The next two chapters move even closer to that experimental objective-first with the SUPREM process simulator (Chapter 2) and then the device simulator SEDAN (Chapter

3).

1.7Exercises

1-1 Using the data given in Figures 1.8 and 1.9, determine the fraction of boron that ends up in the oxide. Does the boron in the oxide and silicon add up to the implanted dose? (Hint: Consider the substrate doping also.)

1-2 Consider the boron profile shown in Figure 1.14. Assume a constant substrate doping of 9 x 1014 cm-3 . Using a Gaussian profile (Eqs. (2.2-2.3)) with peak concentration Px = 1.3 X 1016 cm-3 and a characteristic length of (7 = 0.3 Jim (centered about the estimated projected range, Rm , from the figure), integrate the function from the oxide interface to infinity and compare the value with that specified in the process flow. Suggest explanations of the difference and comment on how good the fit is to the data.

1-3 Consider the net n-type profile shown in Figure 1.15. Assume that the phosphorus is roughly constant in the substrate with a value of 5 x 1015 cm-3. Explain the dip in net n-type doping near the surface. Using data provided in Exercise 1-2, try to evaluate your answer semiquantitatively (i.e. ±30%). Adjust the phosphorus concentration to improve the fit and comment on the process control issues involved. That is, what will happen if n-well and/or threshold implant doses vary by ±10%?

1-4 In Chapter 2, we will use SUPREM III to simulate the various CMOS cross-sections shown in Figure 1.18 (a). While all cross sections receive the same total thermal cycles, the ambient and doping conditions are different. Figure 1.18 (b) shows a "tree" structure representing the inheritance of identical process data from previous steps. Using masking steps as the branch points, write a detailed list of steps for:

a)psub, nch, nch.ch, and nch.sd

b)nwell, pch, pch.ch, and pch.sd

c)nfield

d)pfield

1.8References

[1.1] 1. W. Nagel, "SPICE 2, A computer program to simulate semiconductor circuits," ERL Memorandum ERL-M520 University of California, Berkeley, May 1975.

[1.2] H. J. DeMan, R. Mertens, "SITCAP - A simulator of bipolar transistors for computer-aided circuit analysis programs," IEEE ISSCC Technical Digest, Paper 9.2, pp 104-105, Feb. 14-16, 1973.

[1.3] P. H. Langer, J. I. Goldstein, "Impurity redistribution during silicon epitaxial growth and semiconductor device processing," J. Electrochemical Society, Vol. 121, No.4, p. 563, April 1974.

[1.4] D. A. Antoniadis, S. E. Hansen, R. W. Dutton, and A. G. Gonzalez, "SUPREM I-A program for IC process modeling and simulation," Stanford Technical Report, No. 5019-1, May 1977.

[1.5] D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, "SUPREM II-A program for IC process modeling and simulation," Stanford Technical Report, No. 5019-2, June 1978.

[1.6] C. P. Ho, J. D. Plummer, S. E. Hansen, and R. W. Dutton, "VLSI process modeling - SUPREM III," IEEE Trans. ED, Vol. ED-3D, No. 11, pp. 1438-1453, Nov. 1983.

[1. 7] Z. Yu and R. W. Dutton, "SEDAN III-A generalized electronic material device analysis program," Stanford University Electronics Laboratories Technical Report, July 1985.

[1.8] H. K. Gummel and H. C. Poon, "An integral charge control model of bipolar transistors," Bell Systems Technical Journal,

Vol. 49, p. 827, 1970.

[1.9] M. E. Law, C. S. Rafferty, and R. W. Dutton, "New n-Well fabrication techniques based on 2D process simulation," IEEE IEDM Technical Digest, Paper 20.1, pp. 518-521, Dec. 1986.

[1.10] J. J. Ebers and J. L. Moll, "Large-signal behavior of junction transistors," Proc. IRE, Vol. 42, p. 1761, 1954.

[1.11] D. A. Hodges and H. G. Jackson, Analysis and design of digital integrated circuits, New York, McGraw-Hill, 1988.

[1.12] 1. C. Parrillo, R. S. Payne, R. E. Davis, G. W. Reutlinger, and R.1. Field, "Twin-tub CMOS - A technology for VLSI circuits,"

IEDM Technical Digest, p. 752, 1980.

[1.13] John Shott, Stanford University, private communication.