Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

exponent for linear rate pressure dependence: 0.75000

Figure 1.9: Output based on the field threshold adjustment SUPREM simulation input shown in Figure 1.8. (a) lists the physical parameters used in the simulation,

Figure 1.9 shows a typical program output for the MOS threshold adjustment simulation sequence. Many valuable parameters are listed and it will take several examples before the user is completely comfortable with their meaning. Junction depths are given, and we can see exactly how much oxide has been grown. The integrated dopant concentration tells us how many dopant atoms are contained in each layer. Thinking back to the discussion in Section 1.3, this lets us see exactly how much of the originally implanted boron has been removed to the oxide. Other data extracted from the doping distributions include sheet resistance and capacitance of various layers.

1.4.3Data Transfer from Program To Program

Through well-defined data exchange formats, the various levels of CAD can be linked quite efficiently. The linkage of process to device CAD occurs through the exchange of both topographic information and arrays of data representing dopant distributions. Figure 1.10 shows the commands used by SUPREM III and SEDAN III to store and exchange data. The "save" and "load" commands are used as scratch-pad or permanent storage of SUPREM results. The "export" command allows

save the results for further analysis and plotting

End Suprem-III

Figure 1.9: (Cont'd) (b) gives computed parameters such as oxide thickness and integrated doping (graphics outputs shown in Figure 1.6).

data to be transferred directly from SUPREM to SEDAN for subsequent device analysis. In later chapters we will exploit these communication links to allow coupled process and device analysis of various technology cross-sections.

1.4.4Future Considerations

The above example related to SUPREM file formats (save, load, and export) represents an early stage of evolution of program interfaces. Recently there has been growing concern for unifying program interfaces and standardizing the procedure so that systems of TCAD (Technology CAD) tools can be more easily integrated. The exact nature of what will emerge as a standard is still being discussed. In Chapter 3 the

Figure 1.11: Technology cross-section for CMOS evolved from p-channel, metal gate MOS technology.

a common base of understanding; then more specifically in terms of Stanford's version of the technology. The remainder of the text builds on this basic level of understanding to explore the process and device implications of the various aspects of CMOS processing.

1.5.2Technology Evolution

The evolution of CMOS technology has been driven by several forces. Early CMOS technologies were motivated by the desire for compatibility with existing MOS technology, which is not surprising since CMOS evolved from single channel MOS. As CMOS developed, device optimization, as well as compatibility with existing MOS, became important. This section introduces and presents the relative merits of three specific CMOS processes: p-well, metal gate CMOS; n-well, polysilicon gate (poly-gate) CMOS; and twin-tub poly-gate CMOS.

p-well, metal gate CMOS evolved directly from n-substrate, metal gate MOS (which was the first successful MOS technology). The basic features of the process, illustrated in Figure 1.11, are as follows. First, the p-well is created to counterdope the n-type substrate. For typical substrate doping of 2"" 5 X 1015 cm-3 , a p-well doping of greater than

1016 cm-3 is needed to achieve adequate control over process variations. Additional channel-stop diffusions are added to increase threshold voltages in the isolations regions. The source and drain diffusions for both the p-channel and n-channel devices are created and the gate oxide is grown. Finally, the metal is deposited both for gates and to make necessary bulk contacts. The source-drain regions are defined before creating of the gate, so the gate must substantially overlap the source and drain regions in order to guarantee an inversion over the entire channel region. This leads to non-scalable parasitic metal overlay capacitance and is a major disadvantage of the metal gate approach.

A potential advantage of the p-well process is that the area and speed of the n- and p-channel devices are balanced. Speed is balanced because although n-channel mobility is a factor of 2.5 larger than p-channel mobility, the n-channel device sits in a counterdoped well which degrades its device performance. The result is that for roughly equal area devices in the p-well process, n-channel device performance has been degraded to make it about the same as the optimized p-channel device performance. The advantages of having balanced n- and p-channel devices are currently being offset by the use of dynamic circuit techniques in which complementary clocks are used first to precharge outputs and then to enable the inputs of complementary channel pulldown devices. Further details of this technique can be found in a circuit design text such as Hodges and Jackson [1.11]. The end result is that dynamic speed is optimized by having the fastest possible pulldown devices. In this case, the degraded n-channel performance of the p-well process becomes a limiting factor.

Now let us consider the n-well, poly-gate technology illustrated in Figure 1.12. This process is based on an nMOS, p-substrate, poly-gate technology which is the industry standard for nMOS. In this process, the n-channel device performance is optimized, and it is the p-channel device which suffers from performance degradation by sitting in a counterdoped well.

p-channel performance in this process can be as much as 5 times lower than n-channel performance. Given circuits which are carefully designed using dynamic techniques, this problem can be a second order concern. However, the degraded p-channel performance will lead to a large area penalty if one tries to make the p- and n-channel device have equal current-drive capabilities.

The well and isolation regions in the n-well process are formed in a

Figure 1.12: Technology cross-section for CMOS evolved from an n-channel, poly-gate technology.

similar manner as described for the p-well process. Then, in contrast to the metal gate process, the gate region is defined by first growing a pad oxide layer of thickness of the desired gate oxide. Threshold adjustment implants are subsequently performed through this pad oxide. A doped poly layer is then deposited on top of the oxide. The n+ and p+ source/drain regions are diffused with the patterned gate polysilicon/oxide masking the channel region. Overlay capacitance in this selfaligned technique occurs only due to side diffusion of the source/ drain regions under the gate. Since the source/drain diffusion and gate masking steps are intimately connected, the tolerances on transistors can be scaled in a coordinated way, and greater device density can be achieved. Another ad vantage of the poly gate is that a single poly stripe can define the gates for both n- and p-channel devices, although there is a work-function constraint imposed by having the same poly doping for the gates of both n- and p-channel devices. n+ doped polysilicon is usually the best choice for the gate, yet it has rather serious negative drawbacks for the p-channel device. These effects will be discussed further in Chapter 5 of this book. Another negative property of the poly gate is that the sheet resistance of polysilicon is orders of magnitude higher than metal. This problem can be overcome by adding extra

ALUMINUM

p. SUBSTRATE

Figure 1.13: Technology cross-section for twin-tub CMOS where independent n- and p-wells are used to optimize performance of both devices.

process steps to add metal or silicide on top of the poly gate.

As the final example in our overview of CMOS technologies, we will consider the twin-tub CMOS approach. The twin-tub process was first reported by the Bell Labs group [1.12J. They introduced complementary wells as a means to independently optimize both p- and n-channel devices. Figure 1.13 shows a representative cross-section of the technology. Starting with a p+ substrate, lightly doped p-epitaxial material is grown (one can also consider an n+ substrate with n-epi). Using the selective oxidation mask as an implant mask, first the n-well is implanted. After local oxidation and removal of the nitride mask, the p-well is implanted using the field oxide as a mask. The result is a selfaligned set of complementary wells in which one can proceed to independently optimize the performance of both transistors. By keeping the epi doping sufficiently low, the adjustments of doping in both wells can be independently controlled and thereby not to appreciably degrade the performance of either device. Also, by using a heavily doped substrate, the parasitic resistance can be dramatically reduced. This resistance can have an adverse effect on latch-up [1.11J. Hence, the addition of the epi step on a heavily doped substrate gives an extra degree of freedom. Subsequent to the formation of the epi and twin-tubs, the processing follows the basic pattern discussed for the n-well poly-gate technology.

a radical departure from more conventional nMOS processes. There are many factors to be considered in choosing to go with a single-well versus a twin-tub approach. If an epi approach is used, still further considerations must be reconciled. Certainly defects and yield are at the top of the list, although wafer manufacturers are now providing quality material at an acceptable price. Of equal concern is the fact that processing of epi wafers can give substantially different diffusion results than for the same diffusion steps into bulk wafers. Even though chemical purities for silicon epi are excellent, the defect structures are different than for polished single crystal wafers. Thus, at a minimum one is required to re-calibrate process cycles which worked previously for bulk wafers. Another unusual problem with epi is the differences between lightly doped n on n+ versus p on p+. Initially, there were observed differences in defect structures. More recently there is evidence that even after epitaxial growth, the diffusion properties of p- and n-type dopants is not identical for the two systems. Again, one is faced with a problem of process calibration depending on which substrate type is being used. Thus, although there are major advantages in going to a twin-tub CMOS process, from a design point of view, this technology has characteristics of its own which must be carefully considered. Although it appears quite likely that some twin-tub approach will succeed in the long run, the short term will continue to reflect a diversity of technologies including some metal gate and dominantly silicon gate CMOS. The n-well type technology has many simplicities in its favor and a substantial background of wafer processing know-how for the nMOS technology.

1.5.3 The Stanford CMOS Process

This section presents the details of the fully-implanted 2 {tm poly-gate, n-well CMOS technology developed and implemented at Stanford University [1.13]. Details of the process steps are included here as a preliminary overview of the technology and as a reference for later chapters in which the fabrication sequences will be discussed in greater detail.

Figure 1.12 shows a cross-section of the n-channel and p-channel devices along with vertical lines running through the cross-section at