Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

in cycle consisting of ~ 15 min at 1000°C is required to achieve npn transistors which display good values of f3 with reasonably low levels of emitter-base leakage.

Because boron diffuses significantly more rapidly than boron in single crystal silicon and because we wish to avoid boron penetration through the gate oxide, we perform this high-temperature emitter drivein prior to masking and implanting the boron which forms the base contact, the p-channel drain/source, and the p+ polysilicon gate. We next apply the Polysilicon Resistor mask which is used to remove the SbN4 on top of those poly areas where we wish to avoid selective tungsten deposition. The sheet resistance of the p+ poly resistor (without

to grow about 300 A of oxide on the single crystal drain/source regions and on the exposed sides of the polysilicon in order to prevent selective tungsten deposition in these regions.

At this point in the process, we are ready to etch off the SbN4 in preparation for the selective W-CVD. Two additional factors which should be included in the process prior to this time, however, which are not readily apparent in the cross-sectional drawing are the need that the backside of the wafer is covered with oxide to prevent tungsten from depositing on the backside and the addition of an argon backside damage implant for gettering purposes.

The next major process step is the selective deposition of tungsten on all of the exposed polysilicon surfaces. We have performed this selective W-CVD deposition in a Tylan hot-wall LPCVD tube, a Genus cold-wall reactor, and in a Spectrum cold-wall reactor. Our initial deposition process used the reduction of WF6 in a H2 ambient. However, because the hydrogen reduction process consumes some of the underlying polysilicon, we observed more junction leakage than was desirable. More recently we had added a small amount of SiH4 to the gas stream in order to reduce the amount of polysilicon consumed in this process and yet are able to maintain good selectivity. We aim to deposit roughly 1000 A of W which results in a sheet resistance of roughly 1-1.5 fl/O. This layer forms a low resistivity strapping layer to make the polysilicon/tungsten sandwich a very good local interconnect layer. It also shorts out any possible n+ /p+ diodes in the polysilicon. One of the challenges in this process is to maintain selectivity of deposition when a significant fraction of the wafer is exposed polysilicon - many of our

350 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

designs have exposed polysilicon approaching 50% of the total surface area of the wafer.

At this point, the wafer cross-section is shown in Figure B.1. Because of the oxidation sensitivity of the tungsten and the desire to avoid forming WSh, we must avoid any high temperature processing beyond this point. Loading and depositing an initial layer of LTO at 285°C (followed by a thicker deposition at 380°C) has proven to be a successful means of forming the dielectric beneath metal 1 without oxidizing or otherwise degrading our tungsten film. One of the great strengths of this process lies in the fact that the structure at this point is to be exceedingly planar. The worst case step occurs at the tungsten/polysilicon edge at the MOS drain/source edges and is less than 2500 A. in height. At poly edges which are framed by the locally oxidized poly, the step height is significantly less than this. For this reason, we find that we get adequate step coverage from a 5000 A. thick layer of LTO as our dielectric beneath metal 1 without resorting to reflow or other planarization approaches. Furthermore, by thinning this dielectric, we are able to use a metal 1 deposition of 5000 A. of 1% Si/Al (sputtered at 350°C). This, in turn, greatly eases the problems associated with depositing and planarizing the inter-metal dielectric and depositing the second level of metallization.

Following patterning of our first layer of aluminum we deposit 1.25 J.l.m of LTO as an intermetal dielectric. The first 2000 A. of this layer are deposited at 300°C in order to minimize hillock formation followed by the remaining 10500A. deposit of 4% phosphorus doped LTO at 380°C. We then planarize this structure by performing an unmasked etch back of the intermetal dielectric which removes 5000A. of Si02 • Vias are dry etched in the dielectric followed by the deposition and patterning of

1.0 J.l.m of 1% Si/AI.

B.5 Electrical Characteristics

A Gummel plot for a typical 4 J.l.mx2 J.l.mm emitter npn with a single base contact is shown in Figure B.3. It has f3 = 50, a nearly ideal base characteristic and a value of Rc = 650 il, as determined by the onset of saturation at VCE = 1 V. The measured IT for a 3 J.l.m x 1.5 pm emitter npn with a single base contact is shown in Figure BA [B.5]. For VCE = 2 V, a peak value of IT = 4.2 GHz is observed at a collector current of

352 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

4

N

~ 3

->-

10"

Ie (Al

Figure B.4: Measured IT of a 3 /-Lm x 1.5 /-Lm npn transistor vs. collector current. For VCE = 1 V (lower curve) the peak IT = 3.5 GHz occurs at Ic = 250/-LA. For VCE = 2 V (upper curve) the peak IT = 4.2 GHz occurs at Ic = 330/-LA.

necessitate small values of CBC and Ccs in order to achieve reasonable switching speeds.

Figure B.5 is a plot of the stage delay of several CMOS and BiCMOS ring oscillators as a function of load capacitance. Figure B.6 is a plot of the ECL propagation delay of 47 stage ring oscillators (Fa = 1) for 3 different resistor sizes, VEE = -5 V, and ~V = 500 mV . In each gate the current consumed by the differential pair is equal to the current consumed by the emitter follower.

In conclusion, we have developed a BiCMOS process designed for bipolar-intensive circuit applications. This process features triple-diffused npn transistors and a single level of tungsten-strapped poly for all MaS gates, emitters, base, collector, and drain/source contacts. The resulting bipolar devices (fabricated at drawn feature sizes of 1.5 and 2.0 /-Lm) demonstrate good planarity, high device packing density, low parasitic collector-substrate and collector-base capacitances, and subnanosecond switching time of ECL gates when operated at modest power levels (::; lmW/gate).

Vee _5V T-300K

2.5 W.30j1m AE• 4x4JLm

Load capacitance CL (pF)

Figure B.5: Performance (tpd) of CMOS and BiCMOS 2-input NAND ring oscillators as a function on load capacitance (CL).

B.6 References

[B.1] G. L. Patton, J. C. Bravman, and J. D. Plummer, "Physics, Technology, and Modeling of Polysilicon Emitter Contacts for VLSI Bipolar Transistors", IEEE Transactions on Electron Devices, ED-33, pages 1754-1768, November, 1986.

[B.2] Judy L. Hoyt, "The Application of Rapid Thermal Annealing to Arsenic Implanted Single-Crystal and Polycrystalline Silicon", Ph. D. Thesis, Stanford University, November, 1987.

[B.3] Theodore 1. Kamins, "Effect of Polysilicon-Emitter Shape on Dopant Diffusion in Polysilicon-Emitter Transistors", IEEE Electron Device Letters, Volume 10, Number 9, pages 401-404, Septem· ber, 1989.

[BA] J. M. C. Stork, "Bipolar TransistoT Scaling for Minimum Switching Delay and Energy Dissipation", 1988 IEDM Digest of Technical Papers, IEEE Electron Devices Society, pages 550-553, December, 1988.

354 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

0.8

__ Poly R.sistors

0.7

Q)

Cl 0.6

.~s 0.5

(J)

g'

W 0.4

>. nI

a;

a 0.3

Power I stage (mW/stage)

Figure B.6: Stage delay vs. power/stage for 47-stage ECL ring oscillators (FO = 1). Emitter size = 4 pm x 2 pm and ~V = 400 mV.

[B.5] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, "A New Straightforward Calibration and Correction Procedure for 'On Wafer' High Frequency S-Parameter Measurements (45 MHz - 18 GHz)", 1987 Bipolar Circuits and Technology Meeting, IEEE Electron Devices Society, pages 70-71, September, 1987.

Appendix C

Templates for PISCES Simulation

In this appendix, we will provide several sample input files for PISCES to perform ID analysis. Since these files have virtually molded the functionality of SEDAN into PISCES, we call them templates for ID simulation. It is obviously advantageous to perform ID analysis for those devices which operate largely in a one-dimensional nature because it is much easier to construct a rectangle mesh with very little number of grids (ideally two grids) in the direction which is perpendicular to the current flow while to maintain any necessary number of grids in the device operation direction to achieve both computation efficiency and revelation of the device detailed feature. Actually, the main theme of this book addresses bipolar transistors and MOS capacitors, which all can well be characterized using ID simulation. Even though, 2D analysis is in any sense more general than its ID siblings, it is not necessarily straightforward and efficient for a generic 2D simulator to perform ID analysis. The major challenge lies on the placement of the electric contact to the lateral side of the semiconductor slab which constitutes the bulk of the ID device. For example, in the simulation of the bipolar junction transistor (BJT), if one is to put the ohmic contact to the base region in the intrinsic part of the device, the presence of this close contact will immediately distort the device operation - instead of traversing the base region to the collector region, the injected minority carriers from the emitter will mostly be "sucked" by such a base contact. On the other hand for ID simulator such as SEDAN, the base contact

356 APPENDIX C. TEMPLATES FOR PISCES SIMULATION

is used to control the quasi-Fermi level of the majority carriers in the base region, and it will not interfer the flow of the injected minority carriers from the emitter. So in the sense, this base contact should be not an "ohmic", rather it should act like a "biased" contact towards one particular type of carriers. Fortunately, PISCES', be Stanford's version or industrial variations, all provide the capability of specifying the contact as Schottky which can have different surface recombination velocities (SRV) for different types of carriers. This contact specification can easily be adapted to let the lateral contact to interact with one type of carriers only, thus achieving the goal of putting "biased" contact. In the following two examples for BJT simulation, the SRV at the base

template preserves all the major features of a BJT operation.

It should be noted that this technique does not work efficiently for the source contact to a MOS capacitor, and we are forced to put a heavily doped region to mimic the source region. But even in this case, because of the narrowness of the channel region, it does not incur much burden in constructing the mesh, though the efficiency is lost a bit.

We will present two examples for BJT and one for MOS capacitor simulation in the next two sections.

The doping profile for the BJT is inputed in two ways - by ASCII data files and by the SUPREM "export" binary file. In the first example, an npn transistor with buried and epitaxial layers for collector is simulated. The profile is specified using ASCII data files and the structure is purportedly optimized. The Gummel plot with VeE fixed to 1.5V is simulated and plotted.

File bjtld.pis:

Title lD npn Using Doping Data File

option plotdev=xterm

y.m n=250 1=2.5 r=1.0

region num=l ix.1=1 ix.h=2 iy.1=1 iy.h=250 silicon

dop ascii p.type infil=npn.b x.I=O x.r=l dop ascii n.type infi1=npn.p x.1aO x.r=1 dop ascii n.type infil=npn.as x.I=O x.r=l

contact num=2 surf.rec vsurfn=leO vsurfp=le7

symb newton carr=2

model temp=300 srh auger conmob fldmob bgn method it1imit=10 trap p.to1=1.e-8 c.to1-1.e-8

p1ot.ld x.s=O x.e=O y.s=O y.e=2.5 dop abs log

log ivfi1=bjtld.iv

solve ini outfi1=bjtld.ini solve v2=O.4 v3=1.5 proj

solve v2=O.6 v3=1.5 vstep=0.05 nstep=8 e1ect=2 proj

p1ot.ld x.a=v2 y.a=i3 log p1ot.ld x.a=v2 y.a=i2 log unch

end

The outputs (plots) are shown in Figs. C.l.

C.1.2 npn Transistor from Stanford BiCMOS Process

In this example, the npn transistor cross section in Stanford's BiCMOS process is first simulated using SUPREM, and the simulated doping profile is then fed to PISCES for simulation of cutoff frequency, h. Two schemes - low frequency and frequency dependent ac analyses - can be used for the evaluation of fT. Results are also compared.