Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

Table B.1: Target bipolar device parameters provided by the Stanford circuit and system design community.

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Figure B.1: Cross-sections of the npn transistor and the NMOS transistor - excluding first and second levels of metallization - resulting from the Stanford BiCMOS process.

B.3 Overview of the Stanford BiCMOS Pro-

cess

Figure B.1 shows acornpleted cross-section of the vertical npn transistor and the NMOS transistor that result from our BiCMOS process. A number of the key features of this technology include:

• A single level of polysilicon is used for emitter contacts, base contacts, collector contacts, n- and p-channel gates, and n- and p-channel source/drain contact regions. This allows us to produce high performance polysilicon emitter bipolar transistors coupled with dense, low capacitance contacts to all regions .

• n+ doped poly is used for emitter contacts, collector contacts, n-channel source/drain contacts, and n-channel gates.

•p+ doped poly is used for base contacts, p-channel source/drain contacts, and p-channel gate regions. In particular, this avoids problems associated with buried channel p-channel devices which are frequently encountered when n+ polysilicon is used as the gate material for p-channel devices.

•Selective tungsten is used as a strapping layer on top of all polysil-

«2 n/D)

local interconnect layer and to short out any possible n+ /p+ diodes occurring in the polysilicon layer.

•Local oxidation is used to pattern most of the polysilicon regions. In particular, this results in an exceedingly planar surface after all polysilicon processing. This, in turn, greatly eases the task of adding two levels of metallization to this structure. Furthermore, the local oxidation of poly enables us to produce overlapping contact holes (Le., non-dog-boned poly) between first metal and underlying polysilicon structures further increasing the packing density of this technology.

B.4 Step-by-step Development of the BiCMOS

Process

The following pages contain a step by step description of our BieMOS process. Wherever possible we have included important process parameters (doses, energies, temperatures, times, etc.) as well as resulting physical and electrical parameters (oxide thicknesses, junction depths, and sheet resistances). Wherever possible, we have also attempted to include a discussion of some of the trade-offs which were made during the development of this process.

The initial starting material for this process is p-type (100) borondoped wafers that are 100 mm in diameter. For improved latch-up immunity, we use heavily doped substrates with a 15-17 J.Lm thick layer of p-type epitaxial material grown on top of them. As in our conventional CMOS process, the resistivity of our epitaxial material is 15 ncm (Le., a boron concentration of 9 x 1014 cm-3 ).

An initial oxide which is 2350 A thick (lOOO°C, 32 min, wet O2 ) is followed by patterning with the n-well mask (Mask #1). This, in turn, is followed an oxide etch, resist removal, and the n-well implant -

342 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

phosphorus at 100 keV and a dose of 2.5 x 1012 ionsjcm2 . This implant is annealed and re-oxidized at 1000°C for 30 min followed by the bulk of the heat treatment consisting of 960 min at 1150°C. This drives in the n-well to a depth of 4 J.Lm with a peak surface concentration of 1 x 1016 cm-3 .

The collector mask (Mask #2) is applied next followed by an oxide etch, a resist strip and the collector implant. The collector implant is phosphorus at 100 keV at a dose of 3 x 1013 ionsjcm2 • This implant is annealed and driven in for 200 min at 1100°C. This results in a junction depth of roughly 2.0 J.Lm, a sheet resistance of 430 njD, and a peak surface doping concentration of ~ 3 x 1017 cm-3 .

The characteristics of this collector region are important in determining the overall characteristics of the triple-diffused npn transistor. We would, of course, like the sheet resistance of the collector to be as small as possible in order to add a minimum of series collector resistance. However, we cannot increase the surface doping concentration too much because we will increase the capacitance of the base-collector junction, reduce the breakdown voltage of the base-collector junction, reduce the f3 and base width control of the npn, increase the output conductance of the npn, and increase impact ionization at the base-collector junction. We have also had to deal with a similar set of trade-offs in determining the junction depth of the collector: A shallower collector increases the series collector resistance, decreases the punchthrough voltage of the substrate pnp, and increases the f3 of the substrate pnp. However, increasing the collector junction depth will increase the collector-substrate capacitance and reduces the overall packing density by increasing the surface area consumed by lateral diffusion. Although these trade-offs are more difficult than that commonly encountered in the design of a conventional buried layer process, one advantage of this approach is the fact that the use of a more heavily doped collector region should delay the onset of high-level injection effects in the device.

In our first-generation BiCMOS technology, we have not explored the use of a common implant and drive-in for both the n-well and collector regions. However, subsequent technological development of highenergy implantation and low Dt processing are allowing us to produce a common retrograde n-welljcollector which should meet the needs of both of these regions. Details of our development of a device using MeV ion implantation to form a quasi-buried layer are described elsewhere.

Following collector drive-in, we strip off all oxide and regrow a thin

Table B.2: Target ion implantation conditions for p-channel threshold adjust, n-channel threshold adjust, and active base regions.

pad oxide of 250 A(42 min, 950°C, dry O2 ) followed by the deposition of 800 Aof LPCVD Si3N4. The p-channel transistor follows the equivalent processing as the n-channel transistor except where explicitly noted.

We next pattern the wafer with the Active Mask (Mask #3) and remove the nitride in all field regions. The resist will be stripped and we will then pattern the wafer with the n-channel field implant mask (Mask #4). This mask will open only those regions which are NOT active regions, n-well regions (including lateral diffusion), or collector regions (including lateral diffusion).t The n-channel field implant is performed next - a boron implant at an energy of 100 keY and a dose of 1 x 1013 ions/cm2. This implant results in an n-channel field threshold voltage of 12-14 V.

We next grow the field oxide using a conventional LOCOS process. This oxidation is a 190 min oxidation in wet O2 at 1000°C and grows 7700 A of oxide (prior to some of the following unmasked oxide etches). Following our conventional CMOS process flow, at this point we remove the Si3N4 and do an unmasked Si02 etch which will remove all of the pad oxide (as well as ~ 400 Aof field oxide). We then grow a 250 Asacrificial oxide in steam at 850°C for 14 min which will remove any "white ribbon" which may have formed during the field oxidation, protect the silicon surface, and serve as an implant mask for both the active base implant and the threshold shifting implant steps.

tIn the original CMOS process we actually used an n-channel field protect lithography on top of the active resist layer. In this way, we could avoid any alignment difficulties in determining the position of the n-channel field implant relative to the patterned nitride region. However, the double lithography has proved to be a troublesome process step - we feel that the alignment accuracy of the Ultratech is sufficiently good that we prefer to do the patterning of the channel-stop implant as a separate lithographic step.

344 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

The next series of masking operations and implants perform the p-channel threshold adjust implant (Mask #5), the n-channel threshold adjust implant (Mask #6), and the active-base implant (Mask #7). In principle, these three masks and implants may be performed in any order. Of course, the active-base implant represents an additional mask relative to the CMOS process. However, because we are using p+ poly for the p-channel devices in this process, we must also use an explicit mask for the arsenic threshold adjust implant that is not required in CMOS processes that use n+ poly for the p-channel devices (and boron for the threshold adjust implant). The details of each of these implants are listed in Table B.2.

Following these implants, the sacrificial oxide is stripped and the

point. We next remove the gate oxide in those regions in which we wish polysilicon to contact the underlying silicon directly using the Buried Contact Mask (Mask #8) - namely in all bipolar device regions and in the drain/source contact regions. We must insure that we don't remove the gate oxide from beneath the gate regions of the MaS transistors either due to misalignment of the buried contact mask or due to pinholes during this masking operation. Our design rules call for the edge of the buried contact mask to be separated by 1.0 pm from the actual edge of the MaS gate.

At this point we deposit an LPCVD sandwich consisting of a 1500 A layer of undoped polysilicon followed by a 300 Alayer of Si3N4 followed by a 5000A layer of PSG (8% phosphorus content). Because we wish to minimize the interfacial layer of Si02 which will form between the single crystal silicon and the polysilicon layer, we have been particularly careful to optimize the load sequence during the LPCVD polysilicon deposition to minimize the time during which the wafers are exposed to air and heat simultaneously. Both the polysilicon and the Si3N4 are rather thin layers. Results show that on-wafer, wafer-to-wafer, and run- to-run uniformities are quite good and in fact are necessary in order to achieve reproducible npn device characteristics.

The selection of the polysilicon thickness represents one of the most challenging trade-ofl's in this process design. We require that it be thick enough to function well as a polysilicon emitter and, of course, to provide a stable work function when operating as a MOS gate. However, it must be thin enough that it can be completely oxidized without requiring

Figure B.2: BiCMOS cross-section after local oxidation of polysilicon. Note: This step patterns the poly silicon in all regions except the active MOS drain/source regions between the MOS gates and the drain/source contacts.

such a large Dt that it drives the active base to a great depth before the emitter is in place. Our current experience indicates than 1500 A is an appropriate thickness to meet these goals. The appropriate ShN4 thickness is also a compromise - it must be thick enough to provide an adequate oxidation barrier during the locally oxidized patterning of the polycrystalline silicon, but it must be thin enough that it does not constitute a significant implant barrier during the doping of the emitter and base handle regions. We find that the thickness of the Si3N4 layer should be approximately 300 A. The thickness of the LTO deposited on the top of the polysilicon/Si3N4 stack is not terribly critical - it is used to prevent our extrinsic base implant from encroaching into the emitter region of the device.

We next pattern the LTO and the Si3N4 using the Poly Oxidation Mask (Mask #9). This mask leaves ShN4 and LTO on top of all of the bipolar device regions where we wish poly to remain (Le., emitter, base, and collector contacts), in all of the regions where polysilicon covers field, and above all active MOS device regions. Note: the separation between gate and drain/source contact regions in the MOS devices themselves will be produced by the Poly Etch Mask (Mask #10). We then re-apply photoresist to the wafers and use the Active Base mask once again in order to implant the boron which will be used as the extrinsic base region. We implant boron at an energy of 80 keY and at a dose of 5 x 1014 ions/cm2 . After stripping the resist and the LTO, we are in a position to pattern the polysilicon by locally oxidizing the wafer for a sufficient time to oxidize completely through the polysilicon layer as shown in Figure B.2. For a 1500 A thick layer of polysilicon, we utilize an oxidation cycle of 200 min in wet O2 at 900°C which grows a

346 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

3700 A thick layer of oxide to insure that we have completely oxidized through the polysilicon layer. This comparatively heavily doped extrinsic base region will ultimately be separated from the emitter by the "bird's beak" which is formed during this local oxidation of the poly. Because our active base is already in the silicon at this point, we are limited in the total amount of heat treatment which we can tolerate and still maintain a reasonable narrow base.

There are a number of advantages to using local oxidation as the primary means of patterning the polysilicon. Significant advantages include:

•We may use a single level of polysilicon for all MOS gates, for emitter, base, and collector contact regions, and for MOS drain/source contacts.

•The planarity of the wafer surface should be very good after polysilicon patterning. In particular, we find that it is good enough to eliminate the need for reflow processing prior to first metal.

•By surrounding the poly with oxide frames, we effectively self-align the subsequent doping steps with this polysilicon pattern.

•Because the poly is surrounded by a thick oxide layer, we are able to allow contacts to the polysilicon which overlap the actual polysilicon patterns (as opposed to contacts which must be totally contained within the poly patterns).

•Because the poly is thin and is coated directly by a layer of SbN4 , feature size loss due to bird's beaking is minimal and quite reproducible.

•Because the poly is everywhere protected by SbN4 , it is wellsuited to a variety of the techniques which will allow strapping of the polysilicon layer with a higher conductivity layer to make it more suitable for a local layer of interconnect.

This approach, however, is not free from it's own set of disadvantages. Potential disadvantages include:

•The Dt required to oxidize through this layer may drive the activebase in too deep and reduce the high frequency characteristics of the resulting bipolar transistors. Fortunately, we have not seen

348 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

energies is critical for both the arsenic and the boron implants - in each case the implant energy must be sufficiently high that it penetrate the Si3N4 layer but not so high that it penetrate the MOS gate oxide and the underlying single crystal silicon. Because this is a fairly narrow energy window, it calls for very precise control of the nitride thickness, the poly thickness, and the implant energy. In the case of boron, we find that the appropriate implant energy is 15 keV. Unfortunately, the minimum energy typically available on the Extrion 350D is 33 keY. We are therefore faced with the choice of implanting BF2 at an energy of 67keV (which results in an effective boron implant energy of 11/49 of the energy of the BF2 ion) or of modifying the implanter as needed to operate in a fashion which decelerates the boron ion from an initial energy of 33 keV to a final energy of 15 keV range. While use of the BF2 approach is simpler because it doesn't require a modification of the machine configuration, it runs the risk of generating a deeper "tail" of higher energy boron due to the dissociation of the BF2 molecule in the drift region between the analyzing magnet and the acceleration column of the ion implanter. For this reason, we find that it is safer to periodically reconfigure the ion implanter into "decel" mode for low energy boron implants.

Another important design involves the appropriate heat treatment required to form the electrically active emitter, base, collector, and drain/source regions. Specifically, in the electrically active drain/source regions (which are implanted directly into the single crystal silicon) we wish to minimize the Dt in order to keep the drain/source junctions shallow to minimize short channel effects. In the current CMOS process, for example, the n+ regions see roughly 30 min at 950°C which results in a junction depth of roughly 0.35/-lm and the p+ regions see roughly 30 min at 850°C which results in a junction depth of roughly 0.5/-lm. At the same time, however, we must form a high quality polysilicon emitter to the bipolar transistor and low contact resistivity to the polysilicon base, collector, and drain/source regions. Patton [B.l] and Hoyt [B.2], however, recommend that significantly higher post-implant anneals are required in order to form high-quality polysilicon emitters because of the need to destroy the interfacial oxide layer which will inevitably form between the single crystal silicon and the polysilicon. Moreover, Kamins [B.3] has shown that the "bird's beak" region of the emitter polysilicon tends to be less heavily doped than a one-dimensional diffusion model would lead us to believe. We find that an emitter drive-