Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

Note that because both F and x are vectors with the same dimension, F x is actually a square matrix of 3N x 3N. The ith row of this matrix consists of the derivatives of the ith equation (Fi) with respect to each variable Xj (j = 1, ... , 3N). This coefficient matrix consisting of all the partial derivatives at the current solution is commonly called the Jacobian matrix. The update vector .!lx can be solved for using the following linear equation

where we have generalized the index from 0 to i = 0,1, ... The next solution is thus

This solution process can be repeated (called iteration) starting from the initial guess, xo, until (and hopefully) the update .!lx becomes smaller than certain preset value (called the tolerance). Further iterations usually do not increase the size of this update. If this situation is indeed reached, we say the NR iteration is converged to the solution because further iteration would not change the solution within the tolerance. If, however, after a number of iterations the update still does not come down below the tolerance, the NR iteration might fail to converge at all. This number of iterations is also set by the user and is more or less arbitrary. The convergence of the NR method is largely dependent on how close the initial guess is to the final solution, and is also partly dependent on how accurately the Jacobian matrix is computed. When the iterated solution is close enough to the true solution, the convergence rate is quadratic, i.e. for each consecutive iteration the magnitude of the error (or the update) is decreased to its square. Because the error is usually measured by the relative value, i.e., II .!lx/x II where II . II represents some kind of norm, for example the maximum of absolute values in .!lXi/xi (i = 1 .. .3N), it is always smaller than one when the iteration approaches convergence. Thus this quadratic rate implies that the iteration is rapidly converged to the final solution. Also, it is worthwhile to point out that the accuracy of the Jacobian matrix is not necessarily critical to the solution to which the iteration finally leads, especially when the iterated solution is in the vicinity of the true solution. This can be seen from Eq. (A.43) that as long as the right-hand-side term (called the residual) is diminishing, .!lxi is approaching zero no matter

what value F x(xi) might be. But the exact computation of the Jacobian matrix helps achieve the quadratic convergence rate possessed by the NR method and the convergence of the iteration. Therefore it is almost mandatory to have the Jacobian matrix computed precisely in any practical implementation of NR method.

As is stated above, to guarantee the convergence of the NR method, the key issue is to choose a good initial guess to start the iteration. There are a number of ways to have an initial guess, based either on physical reasoning (assuming quasi-neutrality at the thermal equilibrium, for example) or on using some numerical techniques. Here we discuss how to predict an initial guess based on the previous solution when the bias is advancing. For this purpose, we need to explicitly express the bias

where bias V can be considered as the parameter while solving for x. Suppose that we have found the solution x at bias V, and the bias is then advanced to V +~V. To find the new solution, x +~x, we expand the function F such that

F(x + 6x, V + ~V) ~ Fx(x, V)6x + Fv(x, V)6V = 0 (A.46)

Thus the update ~x due to the change in bias, 6 V, can be estimated by solving the following linear equation:

Realizing that F x(x, V) is just the Jacobian matrix in the previous solution and hence has already been known, FV(x, V) should easily be evaluated because only a few equations (actually only those on the boundary) are explicitly related to the bias. Thus once x is known for V, the x +~x obtained by solving the above system of linear equations should be a good initial guess to the true solution at bias V +~V. When the nonlinear system behaves linearly near bias V, this "projected" solution would be the exact solution when the bias is perturbed within the linear range.

A.4 Post-Processing Techniques -

Device Parameter Computation

The most common use of device simulators is to find device I - V characteristics and device parameters, although the internal distribution of electrostatic potential and carrier concentrations is also of interest. In

this section we will discuss numerical techniques used to extract the device parameters from known solutions of 'I/J, n, and p. There are gen-

erally two types of device parameters which are of greatest interest to the users. One type is for the small-signal parameters. They are in general frequency dependent. However, we here only discuss the case where the frequency approaches zero or called low frequency analysis. Examples of this type of parameters include the junction capacitances. Another type of parameters are of the extreme nature, such as the breakdown voltage. Some parameters, such as the Early voltage and the cutoff frequency, do not fall in either of the above categories, but their evaluation method is similar to low-frequency, small-signal analysis, and we will discuss their extraction together with the first type of parameters.

We start from a general case that any de device behavior (parameter), d, can be expressed as a function of x, the basic variables. When there is perturbation in the bias, say ~V, the change in d can be found from the partial derivative

The notation of the partial derivative of a scalar with respect to a vector should be understood as a row vector with each element consisting of the derivative of the scalar with respect to each element of the vector. That is

(A.49)

where m is the dimension of vector V. Similarly the notation of the partial derivative of a vector of dimension n with respect to a vector of dimension m is understood as n x m matrix. Thus ad/ax is a vector

of dimension 1 x 3N, and ax/av is a matrix of dimension 3N x m. ax/av can be obtained by solving Eq. (A.47). Because this equa-

tion is linear, the ratio of ~x/~V, as interpreted the same way as for notation ax/av, is exactly the value of ax/av. The evaluation of ad/ax involves simply the analytical formulation of the derivative

of expression d with respect to x. We will see several examples in the following parameter calculation. This approach to the parameter evaluation is essentially the same as the quasi-steady analysis in which two closely separated steady states need to be evaluated in order to know the rate of change, but is more efficient (only one steady state needs to be known) and more accurate (bias change is infinitesimal).

We now consider the evaluation of some device parameters which can be obtained using this method, beginning with the conductance and transconductance of a semiconductor device. For devices with more than two terminals, these conductances and transconductance can be assembled in a conductance matrix. Using the previously introduced notation, we can express and evaluate this conductance matrix as fol-

In the one-dimensional case, the terminal electron current, say at node (grid) 1, is evaluated by using the SG expression (Eq. (A.36)) as

in,1+1/2 = q ~:'~+~2 [n2B (tP2 ~tPI) _ nIB (tPl ~tP2 ) ] (A.51)

The junction capacitance for a diode including both the depletion and diffusion capacitance components is computed by the following formula:

(A.52)

where Q is the integral charge of either electrons or holes over the whole device region, and Vd is the voltage applied to the diode. Using electrons as an example,

(A.53)

where L is the length ofthe device. As is seen from Eq. (A.47), on/oVd is easily computed, and the numerical integral is done by one of the quadrature schemes such as the trapezoid rule.

The cutoff frequency, IT, of a bipolar junction transistor has been discussed in the text (Chapter 6). Numerically it can be evaluated

either by frequency dependent ac analysis or by quasi-steady analysis. We here only discuss the latter.

1

h= -- (A.54) 21rTEC

where TEC is the transit time from the emitter to collector and can be evaluated as follows:

Q refers to the total charge for one type of carriers (either electrons or holes) in the transistor [A.7]. Which type of carriers is to be evaluated has little significance in terms of the results because there always exists an overall charge neutrality condition in the device, i.e.,

(A.56)

We can rearrange the expression of TEC using the chain rule as follows:

aQ (ajC )-1 ax ax

where all the computations are performed under condition of VCB = 0 and the base-emitter bias is used as the activation (perturbation) source.

The Early voltage can be computed using the following formula in the active forward operation region:

. aVCE I

)C --

ajc VBE=const

. (ajc ax )-1

)C ---

ax aVCE VBE=const

(A.58)

Usually the bias condition is taken as VBE = VCE = 0.6 V for silicon npn transistor [A.8].

A.5 Summary

Two essential steps in solving a system of differential equations using digital computers are 1) discretization which transforms differential equations to difference ones; 2) nonlinear equation solver employing iterative methods for which only the Newton-Raphson method is discussed in this appendix. In each step, there are two major aspects to be addressed. For discretization, it is accuracy and numerical stability that are of central concern. For the NR method, it is convergency and computation efficiency which are critical. It should be realized that the Jacobian matrix of a nonlinear system at certain operation point is a perfect linear representation of the original system. Its nse is not limited to the NR iteration. In fact all the low-frequency, small signal parameters of the system and the "projected" behavior if viewed as a linear system can be obtained based on this matrix. Some critical issues concerning the implementation of numerical techniques have not been covered in this appendix. Among them are boundary conditions and normalization (i.e., scaling). The interested readers are referred to [A.9].

A.6 References

[A.1] D. A. Antoniadis, M. Rodoni, and R. W. Dutton, "Impurity redistribution in Si02 -Si during oxidation: a numerical solution including interface fluxes," J. Electrochemical Society, Vol. 126, No. 11, pp. 1939-1945, Nov. 1979.

[A.2] G. E. Forsythe, M. A. Malcolm, and C. B. Moler, Computer methods for mathematical computations, Englewood Cliffs, N.J., Prentice-Hall, Inc., 1977.

[A.3] D. 1. Scharfetter and H. K. Gummel, "Large-signal analysis of a silicon Read diode oscillator," IEEE Trans. Electron Devices, vol. ED-16, pp. 64-77, Jan. 1967.

[AA]J. P. Kreskovsky, "A hybrid central difference scheme for solidstate device simulation," IEEE Trans. Electron Devices, vol. ED-34, pp. 1128-1133, 1987.

[A.5] T. J. R. Hughes, Finite element methods in fluid mechanics, to be published.

[A.6] Z. Yu, "Numerical model and analysis of transistors with polysilicon emitters," Ph.D. dissertation, Stanford University, 1985.

[A.7] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed. John Wiley & Sons, New York, 1982.

[A.8] I. Getreu, Modeling The Bipolar Transistor, Tektronix, Inc., Beaverton, Oregon, 1976.

[A.9] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Wien: Springer-Verlag, 1984.

338 APPENDIX B. BICMOS TECHNOLOGY OVERVIEW

for high-speed off-chip line drivers and on-chip clock drivers. As a result, one can concentrate on bipolar devices optimized for high speed even if they must be biased at high currents (e.g., I-lOrnA) because the small number of these devices will not dominate the overall power consumption of the chip. Furthermore, because the number of bipolar transistors used in any design is typically small, there is little need to make the packing density of the bipolar transistors comparable to that of the CMOS sections. Mark Horowitz and his design team at Stanford, however, are interested in exploring machines which would include either significant amounts of pure ECL logic or sizable sections of merged BiCMOS logic to achieve significantly higher overall system performance than offered by the "mostly CMOS" view ofBiCMOS. This approach requires, in particular, bipolar transistors which are optimized to deliver high performance at modest current densities. This requirement, in turn, requires very small parasitic capacitances - in particular, reducing parasitic capacitance may be more important than increasing the peak value of IT if we are interested in operating circuits at collector currents in the range of 100-300 J.LA. Furthermore, this approach requires that the effective packing density of the bipolar transistors be comparable to that of the CMOS devices.

Virtually all high performance bipolar and BiCMOS technologies make use of conventional buried layer and epitaxial layer bipolar structures. However, there is evidence that in situations where one is interested in large numbers of bipolar transistors operating at modest collector currents that it may be advantageous to consider a triplediffused bipolar technology. At modest collector currents, for example, it may be possible to tolerate the larger series resistances associated with triple-diffused collector regions because they result in lower voltage drops than transistors operated at high collector currents. Furthermore, triple-diffused structures may allow smaller overall transistor sizes for a given lithography which, in turn, should result in a lower overall collector-substrate capacitance. For these reasons we have concentrated our initial efforts on triple-diffused BiCMOS technology. We feel, however, that much of what we have developed in the way of technology and device understanding, particularly in terms of base-emitter structures and metallization technologies, is of use if we decide at a later date that buried layers are indispensable.

From a system perspective, we would like to develop a technology which allows densely packed contact structures - in other words, we