Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

The boron dose used in the process is 3.2 x 1012 em-2 implanted at 130 keY. The resulting devices give VT = 1.0V at VSB = 0 for nMOS and the maximum de current gain of i3F = 250 at VCE = 3.5 V for the npn transistor. Even though the current gain i3F looks quite high, we will soon find that both the MOS and bipolar devices show severe degradation of performance when bias level changes. Figure 7.3 shows the degradation of VT with the increased substrate bias. The simulated channel charge versus Vas with substrate bias VSB as a parameter is shown in Figure 7.3 (a) and the extracted threshold dependence on VSB is shown in Figure 7.3 (b) with data points. The threshold voltage doubles for as little as 1.5V body bias (VSB) and nearly triples at a body bias of 4.0V. In fact, if one is to evaluate the body modulation coefficient, /' (Chapter 3), assuming an average substrate doping concentration of Nsub = 2 x 1016cm-3 (corresponding to CPs = 0.74 V in Eq. (3.1)), the curve fitting of the data using Eq. (3.1) gives /' = 1.55, a rather big number. Clearly, the high boron peak doping causes serious degradation of VT with body bias. By contrast, the boron base peak doping is marginal from the point of view of the Early voltage, even though both the current gain, i3F, and the base-open breakdown voltage, BVCEO, seem reasonable due to the small base Gummel number and the low doping level on both sides of the base-collector junction. The breakdown voltage can be simulated using the technique described in [7.9] and including the impact ionization mechanism in the simulation. The trace of Ic vs. VCE when the base contact is kept open is shown in Figure 7.4 (a), and apparently the breakdown occurs below 30V. The Early voltage is evaluated at VCE = VBE = 0.6 V, i.e. VBC = 0, using the formula of Eq. (A.58) in Appendix A (refer to Figure 7.4 (b)), and the result is VA ::::: 10 V. The key issue involved in this formulation is to compute the output conductance at that bias point. Because both SEDAN and PISCES have the capability of evaluating the de conductance at the time the de solution is sought, the simulation of VA is straightforward and definitive in evaluation. This value of the Early voltage is certainly not acceptable for most analog circuit design applications. Figure 7.5 shows the dependence of the current gain on the applied collector bias for a common-emitter configuration, the significant variation of i3F further confirms the dramatic bias sensitivity for this type of device structure. Given these obvious limitations, it is useful to consider alternative device design structures.

2

Vo• M

(a) Channel charge versus the gate voltage with body bias as a parameter.

3.5

2.5

1.5

0.5

Vsa (V)

(b) Threshold voltage versus the body bias. The

curve fitting using Eq. (3.1) gives r = 1.55 assuming N.ub = 2 x 1Q16 cm-3.

Figure 7.3: Variation of threshold voltage of nMOS as the function of body bias.

(b) Simulation of Early voltage. The bias point to evaluate VA is VeE = VEE = 0.6 V.

Figure 7.4: Simulation of open-base breakdown voltage and Early voltage for triple diffused npn transistor.

300

250

200

Va (V)

Figure 7.5: Variation of peak de current gain (f3F) with the collectoremitter bias.

Several alternatives are possible to reduce sensitivities and also to improve device performance. The most obvious step is to decouple the boron implant for the n-channel threshold adjustment and the npn base implant. Unfortunately this requires an additional masking step. However, this cost does not involve high temperatures and associated clean-up steps, so the increased complexity is modest. Moreover, one can improve both nMOS and npn devices without a major process redesign. Another alternative is to completely re-think the bipolar device objectives and to design the process with these goals in mind. Next we will consider the buried-epitaxial layer process.

7.3Buried-Epitaxial Layer BiCMOS

The limitations encountered in the above triple-diffused process result largely from the overly constrained bipolar design. Namely, the n-well is counterdoped relative to the substrate which raises its doping to a rather high value. Next, since the base must again counterdope the n-well, the net doping value goes still higher. If there were no coupled MOS device constraints, reasonable performance of npn could be achieved. However, the coupled n-channel threshold voltage and body coefficient cause a major problem. As suggested above, it is best to decouple the MOS device constraints as much as possible. The first

suggested solution is to decouple the boron implants for the nMOS and npn device. However, this still leaves a collector doping (and parasitic resistance) controlled by the n-well, which also affects the p-channel device's body coefficient. Hence, a major set of process changes to be considered involve addition of a buried-layer and an epitaxial process to reduce the constraints imposed by the n-well. Figure 7.6 shows the cross section of such a process [7.1]. These particular processes are not completely compatible with the standard n-well CMOS process discussed in Chapter 1. Briefly stated, the process grows a thin (about 1.6 JL) p- -epi layer over an n+ buried layer which has selectively been diffused to the p-substrate, followed by an n-well implantation and diffusion on the epi-Iayer. Because of the buried layer the collector resistance of the npn bipolar transistor is greatly reduced. The performance of the bipolar device is further enhanced by the self-aligned, oxide-walled polysilicon emitter and an independent ion implantation for the base doping, which is decoupled from either of the MOS devices so that the dose can be at a value most suitable for achieving the desired current gain, Early voltage, and other bipolar-transistor parameters. The emitter doping is achieved simultaneously with the n-channel source/drain regions. Finally, the p+ base contact is achieved simultaneously with the p-channel source/drain regions. The process is now described in slightly greater detail.

The process flow begins with the creation of the buried layer (which is also used as a p-channel stop as illustrated by the one on the rightmost side in Figure 7.6) as given by mask step (1), followed by the growth of a lightly doped p-type epi-Iayer. Next the n-well is formed in mask step (2) and this diffusion step also serves to form the collector region for the bipolar device. The next masking step (3) forms the first LOCOS (LOCal Oxidation for iSolation) and boron field implantation can be added before the LOCOS step as indicated by the * shown in Figure 7.6. Next the extrinsic base (or called base-link, base handle) region for the bipolar device is formed as s~own in mask step (4). The nitride used for the first LOCOS is removed only in these extrinsic base regions so that after implantation and cleaning the second LOCOS process can be continued to create two different (field) oxide thicknesses - the thinner of the two represents the extrinsic base region and the emitter region soon to be formed is walled by this thin LOCOS. After this step the nitride and the clean-up oxide are stripped everywhere and a thin gate oxide is grown in the regions where both the n- and

p-channel devices will be created. At this point the n- and p-channel device thresholds can also be adjusted. In mask step (5) the "gate oxide" is now stripped out of the emitter region prior to the polysilicon deposition. Hence, when poly is uniformly deposited on the wafer it directly contacts the silicon in the emitter region (or for that matter anywhere that a so-called "buried contact" is required). Prior to the poly deposition, the intrinsic base region, which is the same for the emitter region in this walled approach, for the bipolar device is created by boron implantation with no extra mask step. The poly deposition step now creates both the n- and p-channel gate regions and the polyemitter for the bipolar device - mask step (6) defines these three devices simultaneously. A subsequent polysilicon oxidation step creates sidewall "spacers" at the gate edges of the MOS devices that allow the creation of LDD-type structures. Mask steps (7) and (8) sequentially create the n+ and p+ regions that provide contact to the various devices. The p+ contacts are done last to reduce the thermal cycle for boron since it diffuses much faster than the arsenic used for the n+ regions. Note that during mask step (7) a small n- region is NOT implanted and it will later become a Schottky diode that can clamp the bipolar device and keep it out of saturation [7.1]. In the case of the n-channel MOS device, the source and drain regions, as well as the gate contact, are implanted with arsenic. For the bipolar device the collector contact is directly implanted into the silicon substrate while the emitter region is implanted into the polysilicon and will then diffuse out of the poly and enter the substrate. The p+ implantation of boron forms both the SID regions (contacts) and dopes the gate contact as well for p-channel MOS. In addition, the extrinsic bipolar base region is also contacted in this step. Mask steps (9)-(13), which are not shown in Figure 7.6, involve the metallization of the circuitry; in this case a three-and-a-half level process is used. The "half" level comes from the polysilicon itself which can serve for local interconnects. The first level of metal forms "ohmic" contacts to the n+ and p+ regions and a Schottky diode with the n- region. Increasingly, for shallow junction technologies silicides such as tungsten silicide (WSi) or platinum silicide (PtSi) are being used for first-layer contacts - both of these materials can withstand subsequent high-temperature processing better than metals like aluminum and have good compatibility with tungsten, which is now a popular metal for vias since selective deposition techniques can be used. That is, tungsten only grows in the regions which contact metal or silicon directly and NOT on

306 CHAPTER 7. BICMOS TECHNOLOGY

Surface n-Well Concentration. I/eM'

Figure 7.7: Design constraint of n-well body doping versus the surface concentration based on reasonable performance of both MOS and bipolar devices.

top of the oxide regions. The process shown only lists up through process step (13) which is the via connection between the second and third metal layers. Mask step (14) would be the top-level metal definition to be followed by the usual "scratch layer" passivation.

Based on the above process flow, there is a rather tight budget for high temperature and long drive-in cycles. Moreover, despite the decoupling of npn and n-channel devices (independent boron implants), the p-channel and the bipolar devices are still interrelated. The constraints imposed by the well doping levels and process steps are suggested schematically in Figure 7.7. The well (bulk) doping values are bracketed by constraints of the p-channel body effect, I, and npn highlevel injection (HLI)in the collector. The surface doping concentration of the well is related to the p-channel threshold and parasitic field threshold. The table shown in Figure 7.8 gives target values for the npn parameters (f3F, VA, and iT) as well as p-channel and parasitic threshold parameters (VT and I). To achieve a field threshold of -15V for an oxide thickness of 7000A, it is required that a surface concentration be about 2 x 1016 cm-3 , neglecting work function difference and fixed-charge effects. Fortunately, the phosphorus segregation during oxidation as well as non-negligible (positively-charged) Qf at the Si-Si02 interface both help shift the threshold voltage towards the negative di-

Figure 7.8: Target parameters for the BiCMOS process as described in Figure 7.6.

rection so that the well surface value, before oxidation, can be below its final value. Using analytic Gaussian profiles in SEDAN/PISCES, it is assumed that a surface doping level of 8 x 1015 cm-3 (representing the well) can be used, coupled with a shallow (boron) surface implant of 2.2 x 1011 cm-2 , to achieve a VT ~ -0.8 V and I ~ 0.6v'V. Assuming Qf = 1011 em-2 the field threshold extracted from the simulation gives VT ~ -18V. In the above discussion we have worked backwards from the field threshold and p-channel body factor to bracket the bulk (and surface) parameters of the n-well. Turning now to the bipolar device, there are five major parameters to consider: current gain, Early voltage, base-collector junction capacitance, maximum cut-off frequency, and the knee current which characterizes the high-level injection in the collector. As will be shown below, these parameters are interrelated. Consider first the current gain and Early voltage, which have the following first-order (for constant doping) dependences on base doping (without taking into consideration the bandgap narrowing):

(7.1)

where JpE is the hole current density injected into the emitter from the