Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

Figure 6.17: Semi-logarithmic plot of IB and Ie versus VBE with carrier lifetime variations shown. Qualitative regions of operation are indicated.

basic TO values and moving toward the higher bias levels, a reasonably consistent set of parameters can be obtained. Figure 6.19 shows typical results obtained using an industrial process. Figure 6.19 (a) shows the results from varying TO and Figure 6.19 (b) shows the effect of varying the bandgap narrowing. Based on these two adjustments, an excellent agreement between measurements and simulation is observed.

The above calibration procedure is an essential step in preparing for the actual design applications. Based on a suitable set of physical parameters, one can proceed to look at design trade-offs of doping profiles to adjust de and ae parameters. In the next chapter the impact of the base doping profile on the critical device parameters such as the cutoff frequency will be examined.

(b)

Figure 6.19: Semi-logarithmic plot of Ie and IB versus VBE with (a) lifetime used as an adjustable parameter, (b) bandgap adjustment [6.4].

6.9Summary

Bipolar transistor carrier transport and the resulting compact models used in SPICE are presented in this chapter. We have reviewed the derivation of key formulations for current flow and charge storage. The material presented is applicable to both the Ebers-Moll and GummelPoon models. Based on this review material the chapter moves on to explore the small-signal (ac) representation and especially important analog circuit design parameters such as Early voltage, cutoff frequency, and the associated high-level injection effects. At the end of the chapter we briefly explore some of the manifestations of the physical parameters on the observed I-V characteristics. While the discussion of parametric variations for the bipolar device is rather limited in this chapter, in Chapter 7 we revisit these issues with the objective of learning the trade-offs for bipolar optimization when incorporated into a CMOS technology.

6.10Exercises

6-1 Consider the n+p diode example given in Chapter 4 (Exercise). Replace the uniform p region with a uniform n region of doping 1015 cm-3. Now add a Gaussian boron profile with the following nominal parameters:

Using SEDAN or PISCES to compute the following quantities.

1. Generate the Gummel plot of log Ie and log IB vs. VBE for o < VBE < 0.9V in 0.005V steps and VeE = 3V.

2.For VBE = 0.7V determine the base Gummel number, GB, as defined in Eq. (6.23). This number is calculated based on the

following expression. Use the GB in Eq. (6.24) to calculate Is and plot IseqVBE/kT on your Gummel plot.

3.At VBE = O. 7V, extract and sketch the first-order dependence of IB on the given Gummel plot.

4.Comment on the regions of derivatives of the first-order model from the Gummel plot and the physical causes.

5.Plot the current gain f3F as a function of Ie on a log-log scale.

6-2 Repeat Exercise 6-1 but increase the n-layer doping to 1016 cm-3 . In each part, comment critically on any differences between the two cases.

6-3 Repeat Exercise 6-1 but increase the base doping by using the following change for the boron profile. Comment critically on difference between the two cases.

6-4 The values of capacitances computed by SEDAN/PISCES are total, including both the depletion and diffusion components. Using the bipolar structure from exercise 6-1, compute the following parameters:

1.For values of VBE between 0 and 0.5V, extract the coefficient TF that best fits the data. Determine the error at each bias due to the GBE term.

2.Over the entire bias range, plot the dependence of GBC on VBE. Use additional plots of carrier distributions versus distance to try to explain the effects quantitatively.

6-5 Repeat Exercise 6-4 for the following changes in doping profiles:

1.Increase the collector doping as suggested in Exercise 6-2.

2.Increase the base doping as suggested in Exercise 6-3 (return the collector doping to it's original value).

Comment critically on how each of the parameters and effects changes.

6.11References

[6.1] J. M. Early, Proc. IRE, 40,1401, (1952).

[6.2] J. van den Biesen and T. Toyabe, "Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices," IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 855-861, Aug. 1988.

[6.3] J. Lindmayer and C. Y. Wrigley, "Fundamentals of Semiconductor Devices," Van Norstrand, Princeton, NJ, 1965.

[6.4] R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, John Wiley & Sons, New York, 1977.

[6.5] S.C. Hu, H.C. Tseng, J.S. Ni, E.A. Wolsheimer, and R.W. Dutton, "Computer-aided design of semiconductor processes and devices," Philips J. Res. 42, pp. 533-565, 1987.

[6.6] S. M. Sze, Physics of Semiconductor Devices, 2nd ed., John Wiley & Sons, New York, 1982.

[6.7] J. J. H. van den Biesen, "A simple regional analysis of transit times in bipolar transistors," Solid-State Electronics, Vol. 29, No.5, pp. 529-534, 1986.

Chapter 7

BiCMOS Technology

7.1Introduction

The preceding three chapters have discussed the process and device effects of diodes, MOSFETs, and bipolar transistors. The underlying theme of CMOS technology was used for each of the device structures considered. In Chapter 1 we introduced several evolutionary versions of technology, including metal-gate p-well, poly-gate n-well, and twintub CMOS. The choice of n-well CMOS as the pedagogical example was one of convenience, owing to Stanford's use of that technology in the early 1980s. In this chapter we consider the evolution of CMOS towards bipolar-compatible CMOS or BiCMOS technology. The possibility of developing BiCMOS is attractive because a number of performance improvements are possible. Namely, the bipolar device offers current driving, device matching, and threshold control superior to MOS. These features have led to high-speed gate arrays [7.1] and static RAMs with superior performance [7.2]. The major disadvantages of BiCMOS are increased process complexity and reduced yield due to emitter-collector shorts. In addition, the merged process can reduce performance of either the best CMOS or bipolar technology by itself. For example, by using the n-well as part of the bipolar device, the process may shift in a direction which raises the body coefficient, " for MOS operation (for details, see section 7.2). Conversely, constraints on epitaxial and base doping levels as imposed by the MOS devices may reduce bipolar performance - for example, lower breakdown voltage and higher output conductance (Le. lower VA). In short, the simultaneous optimization of

Figure 7.1: BiCMOS cross-section where the n-well serves also as a triple-diffused collector.

scale multiplication times - an impressive record for its time [7.6). More recently VLSI versions of the technology have emerged [7.7). The technology cross-section for the n-well BiCMOS version is shown in Figure 7.1. From the figure we see the usual n-well and boron implant for the n-channel threshold adjust. However, for the right-most device we see that the n-well can also serve as a collector region (first diffusion). The n-channel threshold adjustment (p-type doping) can form the base region (second diffusion) for the npn device. The emitter region (third diffusion) of the bipolar transistor is formed sharing the implantation for n+ source/drain regions in the p-substrate. Even so, the two key trade-offs to be considered are as follows:

1.control of bipolar gain and punchthrough with increased boron dose (i.e. the base Gummel number), and

2.alleviation of the n-channel body effect by reducing boron dose.

A typical process specification is listed in Table 7.1. The n-well concentration of 1016 cm-3 sets a rather high "pedestal" which the base counterdoping must compensate. Specifically, the boron dose must give a peak, after diffusion, of greater than 1016 em-3. This part of the profile becomes the bipolar base region. However, because it is also used to adjust the n-channel threshold voltage, the boron peak (greater than 1016 cm-3 ) now controls the body factor for the device. Figure 7.2 (a) and (b) show the boron profile in the n-channel device region and the final bipolar transistor doping profiles. The boron peak for the nMOS device is about 6 x 1016 cm-3 while the surface value is 3 x 1016 cm-3. For the bipolar device, the net peak base doping is about 4 x 1016 cm-3 •