Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

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Figure 5.15: Channel charge vs. gate voltage (solid line) and values scaled by the denominator of the mobility fall-off Eq. (5.88) (dashed line), where e = 0.05 V-l and VTX = VTO = 0.7V.

bility falls-off for increasing Vas owing to mobility reduction. There is still some discussion concerning the detailed physics of this phenomena related to both surface properties as well as the electrostatic potential well that confines the carriers. Nonetheless, the phenomenological result is well modeled using a mobility reduction factor of form [5.5]

where flo is the low-field mobility, and e and VTX are fitting parameters for matching the computed and measured channel conductance at low drain-source voltage. VTx is normally the threshold voltage, i.e. VT(VSB), and its use indicates a threshold dependence. However, to account for the body bias effects, it is often chosen as VTO, the threshold voltage at zero substrate bias [5.5]. e is proportional to the gate oxide capacitance, or the inverse of the gate oxide thickness (tox), from the physical analysis [5.6J. For tox around 1000 A, the value of e is about 0.05 v-to Figure 5.15 (dashed lines) shows the product of charge times the mobility expression given in Eq. (5.88). Clearly such a form can

be used to fit the data. The advantage of using the simulation to fit such curves is the direct coupling of the underlying nonuniform substrate doping effects. That is, the charge curve shown in Figure 5.15 may well have substantial spatial and bias dependences which can be tracked using SUPREM and SEDAN jPISCES. Based on these accurate charge models which can be confirmed using capacitance measurements, one can then properly extract the parameters needed for Eq. (5.88) with some reasonable assurance of their ability to correctly track the technology dependencies. The above examples of subthreshold, capacitance, and large vertical field dependences in MOSFET devices help to illustrate the value of SUPREM and SEDAN jPISCES in these aspects of device modeling. Since the MOSFET is dominantly a 2D structure, we must defer many other topics for consideration in connection with analysis using the PISCES program.

5.6Summary

In this chapter we have introduced the basic concepts of the MOS device - both in terms of its capacitive behavior (Section 5.2) and its channel transport properties (Section 5.3). While many of the 2D field effects and channel transport limitations of the device cannot be modeled accurately using only 1D analysis, we have shown areas where the results are in fact excellent. Specifically, the modeling of threshold voltage as well as subthreshold and capacitive behavior are all excellent examples of appropriate application of 1D process and device models. In Section 5.5 we have considered not only these applications but also the extension of the modeling to consider channel mobility degradation for large vertical fields. In conclusion, this chapter shows both the analytical theory of the MOSFET and an important set of suitable applications of 1D process and device analysis of these structures.

5.7Exercises

For the gates, assume that degeneracy applies at the Fermi-level is at the respective band edge.

5-2 Repeat 5-1 but use the substrate doping values of 1015 cm-3 in each case. Comment on differences in terms of practical device applications (good and bad parts).

5-3 Consider the n-channel device for the Stanford CMOS process:

1.Use SUPREM to create the channel doping profile and save and "export" file for further use.

2.Use the "threshold" statement in SUPREM to extract and plot VT vs. VSB for increments of 0.25 V between 0 and 5 V. Note: the expression used for calculating VT is discussed in section 5.4 and the implementation of Antoniadis [5.2] is used.

3.Compare the zero bias (VSB = 0) value with the two corresponding VT'S calculated in exercises 5-1 and 5-2.

4.On the same graph, use Eq. (5.37) and the analytical expression for QB (see Eq. (5.79)) to plot VT vs. VSB for the two cases from exercises 5-1 and 5-2.

5-4 Repeat exercise 5-3 for the case of the p-channel device in the Stanford CMOS process.

5-5 Using the "export" file from SUPREM, load the results into SEDAN or PISCES and compute the following:

1.For VSB = 0 sweep Vas in 0.02 V increments in the range of ±0.2 V of the VT computed in exercise 5-3. Plot the surface channel charge and determine its value at the SUPREM-calculated VT.

2.At the SUPREM-determined VT value of Vas, re-run SEDAN or PISCES and plot net doping, electron concentration, and electric field versus depth. Use Eq. (5.65) and Eq. (5.70) to determine VT.

Hint: use an analytic Gaussian expression to estimate the N A (x) and integrate between limits determined by the surface (x = 0)

and the depletion edge (Xd), use the electric field at that point in the Q B expression.

5-6 Consider the design of a p-channel device using a retrograded n-well as opposed to the counter-doped well used for the Stanford CMOS. Using the following analytical expression in SEDAN/PISCES, compute the following:

1.the threshold for a surface inversion charge of 10-8 Coul/cm2

2.confirm this VT based on the method used in Exercise 5-5.

3.plot VT vs. VSB and determine a ND(average) and cPFn which gives the best fit to the curve using Eq. (5.80).

5.8References

[5.1] G. Baccarani, M. Rudan, and G. Spadini,"Analytical IGFET model including drift and diffusion currents," lEE J. Solid-State Elect. Dev., vol. 2, no. 2, p. 65, 1978.

[5.2] D. A. Antoniadis, "Calculation of threshold voltage in nonuniformly doped MOSFET's," IEEE Trans. Elect. Dev., ED-31, pp. 303-307, March 1984.

[5.3] Z. Yu and X. Zhao, "A semi-analytical approach to the evaluation of threshold voltage in depletion MOS's with nonuniformly doped substrates," IEEE Trans. Elect. Dev., ED-35, pp. 993-998, July 1988.

[5.4] G. E. Forsythe, M. A. Malcolm, and C. B. Moler, Computer Methods for Mathematical Computations. Englewood Cliffs, NJ: Prentice-Hall, 1977.

[5.5] P. Antognetti and G. Massobrio, eds., Semiconductor Device Modeling with SPICE. New York: Wiley, 1981.

[5.6] K.Y. Fu, "Mobility degradation due to the gate field in the inversion layer of MOSFET's," IEEE Elect. Dev. Lett., EDL-3, pp. 292-293, Oct. 1982.

Chapter 6

Bipolar Transistors

6.1Introduction

The previous two chapters have discussed the pn junction, the MOS capacitor, and the FET device. For the pn junction, we considered minority carrier injection into material of the opposite carrier type. In the MOSFET, we create a conducting channel between source and drain regions (both of opposite carrier type to the substrate) by inverting the carrier type of the substrate (or the well). In this chapter we consider the bipolar transistor and its operation in detail. Bipolar transistor operation hinges on the proximity of two pn junctions, separated by less than a diffusion length for minority carriers. If one junction is forward biased and the other reverse biased, it is possible to inject (or "emit") carriers from the forward biased junction and "collect" these carriers at the adjacent, reverse biased junction.

Potential bipolar structures are abundant, even in a CMOS process. Consider again the CMOS cross-section shown in Figure 1.13. Figure 6.1 shows the potential bipolar devices in this structure, both lateral and vertical, in addition to the basic CMOS topography. Since both MOS and bipolar structures can be critical to CMOS operation, we will consider the key operational features of each. From a device simulation point of view, only the vertical structure can be analyzed in detail using one-dimensional simulation tools SUPREM and SEDAN. However, by using suitable approximations in SEDAN, the lateral structure can also be considered. In addition to the predominantly parasitic bipolar devices shown in Figure 6.1, we can purposely alter the profiles

B

B c c

Figure 6.1: CMOS cross-section showing a number of vertical (PNPwellV) and lateral (NPNiL, PNPiL, and PNPwellL) parasitic bipolar transistors.

and spacing to create reasonable high-performance bipolar-compatible CMOS devices (BiCMOS). We will postpone the detailed discussion of this topic until Chapter 7, although the underlying groundwork and modeling concepts will be established in this chapter.

In this chapter we will consider the bipolar phenomena and bipolar junction transistors (BJTs). In Section 6.2 we will extend our discussion of the p-channel MOSFET to introduce the intrinsic lateral pnp device shown in Figure 6.1 labeled as PNPj L. Based on the discussion of charge distributions in this device, we will present a generalized base transport current model for the npn device in Section 6.3. Section 6.4 turns to dynamic charge-storage effects in the bipolar device. This will include the effects of both junction capacitance and injected minority carrier charge. Section 6.5 presents equivalent circuits for device operation in both de (including large signal analysis) ae modes. Section 6.6 discusses the second-order effects on carrier transport in the transistor. Mainly the Early effect, high-level injection and external series resistance effects are addressed. Evaluation of transit time and small-signal parameters in device simulation is then introduced in Section 6.7. The last section (Section 6.8) considers applications of device simulators in bipolar device design.

Both pnp and npn devices are considered in this chapter as well as vertical and lateral devices. While at first this may seem unnecessary and confusing, there is a reason for presenting a derivation of bipolar configurations. Specifically, in current Ie technologies there is an abundance of parasitic bipolar transistors, most of which occur in the lateral device configuration. The intent in the following discussion is to help the reader become more versatile in seeing the effects in a variety of situ ations.

6.2Lateral pnp Transistor Operation

Our discussion of the MOSFET has been based on the assumption that conduction is along the surface of the MOS structure and that the flow of carriers is ohmic (Le., drift current only). We usually assume both source-bulk and drain-bulk diodes are reverse biased. However, an "undesired" current flow can take place if one of the pn junctions becomes forward biased. The flow of this current is not related to the drain current as determined by surface flow under control of the gate. In fact, the current is limited only by the forward-bias voltage applied at, say, the source-bulk junction.

Now we will discuss conditions under which this forward biased junction current flow can give rise to another useful device configuration. Namely, we will consider the pnp (or npn) bipolar junction transistor. To initiate the discussion, let us use the MOSFET structure and apply the biases as shown in Figure 6.2. The primary change from the case of normal bias is the positive source-bulk voltage.

Recall that in a saturated MOSFET, the channel (via the source region) provides holes which are extracted at the drain region. This extraction process is basically that of a reverse biased pn junction. The flow is limited by the hole supply at one end of the channel. For the conditions shown in Figure 6.2 a parallel process can now be described which also involves the extraction of holes at the "drain" terminal. Specifically, for the condition of VSB > 0, holes are injected into the substrate. These injected holes move in all directions away from the p-region, primarily by diffusion, and are recombined with electrons. However, some of these holes will move in the direction of the drain region. If the structure's dimensions are such that holes can reach the drain region before recombining, they can be extracted across the re-

Figure 6.2: Cross section of a MOS device showing two bias conditions: normal FET operation - ID (the solid arrow) under Vas control and bipolar operation - Ie and IB controlled by VSB (> 0) shown by dashed arrows.

verse biased pn junction at the drain. The result is that current can appear at the "drain" terminal (as the collected current Ie) due to injection of holes at the forward biased source pn junction. For the geometry shown in Figure 6.2 it is clear that a majority of the current flow from the "source" feeds only recombination current (shown as IB). A very small frac!ion of the injected holes reach the "drain" and are collected.

Because we are now referring to hole injection and collection, it is useful to define this mode of device operation in the terms shown in Figure 6.3(a). The three regions shown (left to right) previously represent the source, bulk, and drain regions. For the device operation described above, the "source" tends to inject holes so it is called the emitter. The "drain" region serves to collect the injected carriers and hence becomes the collector. The bulk region now becomes the base region. We have omitted the gate region since we will ignore any bias from that region. Now apply bias such as to ground the base and to set a positive bias voltage on the emitter and a negative bias on the collector. Under these conditions the emitter-base junction is forward biased. Note that holes are injected into the base and electrons are injected into the emitter. The dashed lines indicate electron flux direction (the resulting current is in the opposite direction). It can be noted that several components of hole and electron flows are indicated. This is because the different flows give rise to different terminal currents and voltage dependences. Com-

swept out to the collector at the reverse-biased base-collector junction before they can recombine. Component @represents those holes that are injected but recombine in the base before being extracted at the collector. As is indicated in the table of Figure 6.3 (b), this component contributes only to emitter and base currents. Component @ is due to holes and electrons that recombine in the space-charge region of the base-emitter junction. As is indicated in Figure 6.3 (b), this component has an eQVEB/2kT dependence. This result follows from our earlier considerations of pn junctions in Chapter 4. Finally, component @is due to the injection of electrons into the emitter region. This component appears in the terminal current between the base and emitter only. It should be clear that the holes can recombine in several ways instead of simply being collected at the collector. Furthermore, the reverse injection of electrons into the emitter can give rise to a significant portion of the base current. The total current at any terminal is the sum of the several components, which are functions of voltage. The various components of the base current are plotted in Figure 6.3 (c). Both carriers with different polarities, i.e., holes and electrons, participate in the current flow of this transistor, hence the name Bipolar Junction Transistor or BJT.

The BJT is often used as a current gain element as opposed to a voltage-controlled device such as the MOSFET. With this in mind, an important figure of merit for a BJT is the current gain, which is defined as the ratio of the output current (usually the collector current, Ie) to

the input current (either the base current, IB, or the emitter current, IE) as follows:

(6.1)

and

(6.2)

Note that these are de parameters.

Following the "short-base" and "long-base" diode discussion given in Chapter 4, the expression for the several current components can