Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

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Figure 5.10: Extracted VT versus VSB for (a) n-channel device, including idealized plots for constant doping, (b) p-channel device.

Figure 5.11: SEDAN input statements for the n-channel device using analytical profile.

is to use analytic approximations, which is shown in this SEDAN example. The advantage of this approach is the excellent control of variables and the possibility to choose optimum design variables - then subsequently use SUPREM to target the process to meet these optimums. In subsequent design studies we will see how to best use both approaches.

Figure 5.9 (a) shows the simulated Qn vs. Vas curve for the boron implant approximated using the analytic Gaussian profile with parameters given in Figure 5.11. On the other hand, for the p-channel device, the profile obtained from SUPREM simulation (Figure 5.8 (b)) is used to generate Qp vs. Vas curve shown in Figure 5.9 (b). Using these charge curves to extrapolate the appropriate threshold voltages, Figures 5.10 (a) and (b) show the n-channel and p-channel VT versus VSB curves. The results show a dependence quite different from those

predicted by Eqs. (5.80)-(5.81). Namely, the threshold changes rapidly for the n-channel device with small VSB but for larger values the slope becomes smaller, an indication of the nonuniform substrate doping. The observed threshold sensitivity can be understood in terms of the movement of the depletion edge with bias through the nonuniformly doped boron region. Several depletion edges at different substrate biases are shown in Figure 5.8. Clearly, for the n-channel device when VSB > 2V, the depletion edge has reached the lightly doped substrate region.

5.5.2Two-region Model

This body-bias sensitivity of the threshold voltage for MOSFETs with nonuniformly doped substrate can be modeled analytically using simplified doping profile in the substrate. In the following we introduce a two-region model. To avoid ambiguity, we use n-channel MOSFET as an example. Our goals in analytical modeling are to achieve 1) correct threshold voltage at zero body bias (initial value), 2) correct initial slope of VT vs. VSB, and 3) proper asymptotic slope at large substrate bias. We first take a look at the threshold voltage from a step doping profile with doping level Ns and width Xs in the surface region on a uniformly doped substrate of concentration NB. Further, we assume that there might exist a surface sheet doping layer at the Si0 2 -Si interface with amount of dopants DJ (units of atoms per unit area) and having the same dopant type as that in the substrate. Thus, if for the body bias at which the depth of the surface depletion region edge, Xd, is smaller than XS, then

(5.82)

where <PFp = Vtln(Ns/ni) is computed based on the doping in the surface region. And

mined by N s. Knowing the initial slope, one can thus uniquely determine the concentration in the surface region. Moreover, if it is assumed that at the zero body bias, the depletion edge of the surface space charge region falls in the surface region, one can use Eq. (5.82) to calculate DJ

the threshold voltage sensitivity, while too small an initial slope results in underestimating the sensitivity. In Figure 5.12 (a), an initial slope of 0.5 is used, which results in Ns = 1.5 x 1016 cm-3 • And with the above initial VT, the surface sheet doping is determined as D I = 7 X 1010 cm-2, and xs = 0.44 J..Lm. The two-part doping profile is also shown in Figure 5.12 (b).

5.5.3MOSFET Design by Simulation

Figure 5.10 (b) shows the simulated plot of VT vs. VSB for the p-channel device with doping profile shown in Figure 5.8 (b). In contrast to the n-channel case we see an initially-slower increase in VT with VSB which increases for higher bias levels and becomes asymptotically close to the analytic result for ND = 4 X 1015 cm-3 • This change can be understood by looking again at Figure 5.8 (b) and realizing that because of the boron counter-doping of the well region, the low bias depletion region is confined to the more lightly doped region. As the substrate bias increases, the depletion edge moves quickly into the more heavily doped well region. The higher doping increases the slope of the curve of the threshold voltage vs. substrate bias, which has a negative impact on the p-channel device performance. Looking at the problem from a technological point of view, the choices are limited for use of a lower well doping because of difficulties in process control. However, returning to the discussion in Chapter 1 related to twin-tub technology, we can quickly see the motivation to move in this technological direction as it pertains to the p-channel threshold sensitivity with substrate bias.

In addition to the large substrate bias sensitivity of the p-channel device, the combined effect of the channel doping profile and the use of n+ gate material has rather troublesome consequences for the channel mobile charge in the p-channel device. Figure 5.8 (b) shows the inversion charge Psp at zero substrate bias and gate bias of 0.65 V, which is well into strong inversion. While the plot has some of the same characteristics as for the n-channel inversion layer, we can also see some distinctly different features. The most prominent feature is the fact that the hole concentration falls-off over a substantial distance into the substrate. This effect is frequently called a sub-surface or "buried" channel device. One positive aspect of this type of device is the improved channel mobility. Since the peak of mobile charge is moved away from the surface, the carriers experience much less surface scattering and hence

become more mobile. The negative side of the device relates to its "off" characteristics. Specifically, the channel region forms rather easily in the lightly doped region and hence it is susceptible to greater subthreshold and drain-induced-barrier-Iowering (DIBL) effects. Stated more simply, it is more difficult to turn the p-channel device off under these conditions. One technological change which improves the situation is to use a p+ rather than n+ gate. Yet even with this modest improvement, the underlying problem of substrate doping profile is still the major concern. Hence to overcome both the poor substrate sensitivity and buried channel characteristics of p-channel MOSFET devices, one needs to return to the original definition of the well structures and seek a solution with lower surface doping level.

The above discussion has focused on threshold voltage and its sensitivity to substrate bias. We have seen that for practical MOSFET technology the role of nonuniform substrate doping is indeed significant. There are several other aspects of MOSFET design which can conveniently be addressed using one-dimensional analysis. These include: 1) estimates of subthreshold conduction, 2) fall-off of drain current with gate field mobility reduction and 3) gate capacitance estimates for unusual doping conditions. We will illustrate each of this points although details will be left as exercises for further study. Figure 5.13 (a) shows a semi-logarithmic plot of channel charge versus gate bias. The point marked as VTH(O) gives the classical extracted threshold at VSB = 0 as defined by strong inversion. As can be seen clearly from the plot, substantial mobile charge exists at the surface of the device, even below VT. This charge is the so-called weak inversion or subthreshold charge. For ratioed n-channel enhancement/depletion (E/D) technology these subthreshold currents can be significant. For example, for the row select pass transistor shown in Figure 5.13 (b) the subthreshold leakage through M1 can limit storage time for gate charge stored on M2, which represents the storage node. That is, since the gate voltage of M1 is at VOL, the line driver output which is not ground for nMOS, the capacitance of M2 is being discharged via the weak inversion charge in the channel shown in Figure 5.13(a). To first order, the channel conductance is given by

(5.86)

and for a 50 fF MOS capacitance (Ctot = 50 X 10-15 F), W/ L = 10 and fl = 700cm2 /V·sec, and VOL = 0.4 V, from Figure 5.13(a) for VSB = 0

DSsubth

Hence, we can see that this time constraint is catastrophic with respect to the normal refresh time of milliseconds assumed for dynamic memories. Although substrate bias increases the threshold voltage and hence reduces the subthreshold current to a negligible level, as seen for example in the curve with VSB =2 V in Figure 5.13 (a) , but the increase of VT is not desirable.

Generally, the technology development seeks to increase the capacitance of the storage node as much as possible. Figure 5.14 (a) shows the technology cross-section of one such high capacitance (HI-C) cell where an n-type implant has been added in the channel region of a p-type substrate with an enhanced channel doping (nMOS). The insert in the figure shows how the storage node is directly coupled to the row select pass transistor using a double-poly gate technology. Figure 5.14 (b) shows the Qn versus gate voltage plot for this cell. Notice that the threshold voltage is now negative indicating that a channel is formed even at zero gate bias. This results in higher storage node capacitance. From a process design point of view, the SEDAN/PISCES and SUPREM programs can be used extensively here to optimize the technology to meet the design specifications. In summary, then, the circuit shown in Figure 5.13 contains two devices, each with different performance requirements. The use of process and device analysis can be critical in understanding the technology dependence of both subthreshold conduction in the pass transistor (M1) and high-capacitance structures - the equivalent of M2 shown in Figure 5.14 (a).

The actual conduction of current by means of channel charge is a two-dimensional field problem and use of program PISCES are invaluable. Especially when considering effects such as velocity saturation, dynamic charging of the channel, gate capacitance, and output conductance, the full 2D approach is essential. These topics are covered extensively elsewhere so as a final example we will consider the gate voltage dependence of carrier mobility in the channel. Figure 5.15 (solid line) shows a plot of inversion charge versus gate voltage. As we can see, the subthreshold behavior can be observed below the extrapolated VT value. For voltage substantially above VT the plot is highly linear. However, when considering channel conductance, the product of charge times mo-

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Figure 5.14: High Capacitance (HiC) technology and device characteristics, (a) double implanted channel region with device cross-section shown as an insert, (b) Qn versus Ves which shows that the channel already inverted at Ves = OV.