Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

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SUBSTRATE

(a)

(b)

Figure 5.4: The p-channel MOSFET,(a) showing an inversion layer and space charge under the gate (double cross-hatch marks show effect of negative VDS), (b) the inversion layer under uniform surface conditions (Vns small) can be modeled as a surface conductance Gns.

Consider the diagram of a MOSFET shown in Figure 5.4 (a). Let us begin by assuming that the two p-regions and the substrate terminal are at ground potential and a negative potential is applied to the metal gate electrode. We will assume that inversion has occurred uniformly under the region covered by the gate. Hence the figure shows a depletion region (single cross-hatched) extending into the bulk to x::: Xd, from the surface at x ::: O. Along the surface a "p" inversion layer extends from one p-region at y ::: 0, the ~, to the p-region at y ::: L, the drain. Functionally these two regions are interchangeable. For the condition of uniform inversion there is a continuous supply of holes from source

to drain which is called the channel. Hence we can model this channel layer between the source and drain as a thin sheet-charge with terminal conductance GDS. To understand the meaning of a surface conductance, consider the following. Assume that the inversion layer has some constant average concentration, p, extending over its thickness Xinv (see Figure 5.4 (b). To calculate the conductance of this layer along the channel we use the standard resistor formula

Pop

The under-braced product in the above equation represents Pap and has units charge/cm2 • Note that defining P and Xinv is somewhat unnecessary since Pap is the known quantity from our earlier calculations. Using Eq. (5.31),

(5.40)

The subscript "GS" to the bias V is used to indicate that we choose the voltage on the gate with the source potential (which in this case is ground) as our reference. In other words, we have taken Vs =VB =O.

If now we remove the restriction that the drain be grounded, we can pass current through the conductance. That is, the drain current is given by:

(5.41)

To observe this dependence, both VGS and VDS must be negative. We also have shown that VTF is negative. From Figure 5.4(a), for VDS < 0 the source pn junction becomes forward biased and diode current as well as surface conduction will be observed for ID. The dependence of ID on VDS and VGS is shown in Figure 5.5. For a fixed VGS, the drain current increases with the magnitude of VDS as if the inversion layer were a constant conductance. At this point we should consider if this simple conductance model applies for all negative VGS and VDS. The answer

Io (negative)

fHI

Figure 5.5: A plot of IDs vs. VDS with VGS as a parameter. This plot assumes that the surface inversion is adequately modeled as a uniform conductance.

is partially illustrated in Figure 5.4 (a). As VDS becomes more negative we are reverse biasing the drain pn junction, hence the space charge is increasing in this region. The applied potential at the drain also requires that the Fermi level is raised (for negative VDS) at the drain end relative to the source. Assuming that the inversion still exists at every point along the channel, the conduction band position is fixed relative to the Fermi level (it might be more appropriate to say EF - Ev is constant since we are considering surface hole charge). Hence by raising EF with increasing position y, we also alter the surface potential (making it more negative) and increasing the depletion depth. This is shown as the double cross-hatched region in Figure 5.4 (a). Another way to see this effect is to look at how the conduction band at any position in the x - y plane is distorted for VGS and VDS. This representation is shown in Figure 5.6. The first figure shows the topology as viewed from above. The second figure shows the conduction band as a function of the x - y position. The two sections AA and BB show the expected

(a)

(b)

(c)

Vos < 0

(d)

Figure 5.6: MOSFET conduction band surface and band diagrams as functions of VDS and VGS, (a) doping in the regions of intent, (b) band diagrams Vs = VG = VD = 0, (c) band diagrams Vs = VD = 0 given VG, (d) band diagrams given VG and VD.

side-view energy band diagrams we have already considered for the pn junction and MOS capacitor. Figure 5.6 (b) represents VDS = 0 and VGS = O. Upon applying a negative VGS = VTF the bands are bent as is shown in Figure 5.6 (c). The section view across CC shows the usual equilibrium band diagram at strong inversion. In Figure 5.6 (d) we apply a negative VDS, as well as the negative VGS already applied to the gate. For negative bias the bands move up by q\VDsl at the drain while the source and bulk band positions are unchanged. The two orthogonal section views DD and EE show the band diagrams in the Y direction at x = 0 and in the x direction in the drain region (y = L). To describe mathematically how the drain voltage alters the surface charge, Psp, it is useful to write an expression for the surface potential as a function of position y. Before applying VDS, but still having VGS present, the surface potential (between y = 0 and y = L) is uniformly 2<PFn. When VDS is applied the surface potential is augmented by an amount V(y) (which cannot a priori be expected to be linear with y). Thus,

Two known values for V(y) are YeO) = 0 and VeL) = VDS. Examining Eq. (5.26) we can see that the 2<PFn terms must be replaced by <Ps(Y) and as a result Pap is now a function of y. That is, two things happen due to this augmented surface potential. First, the bulk charge term increases (see Eq. (5.28)). Simultaneously, the free surface charge density must decrease since the potential drop across the oxide is less and there is

now more QB. This can be written by using Eq. (5.42) in Eq. (5.26) in place of 2<pFn:

(5.43)

Notice that the bulk depletion charge is greater than that obtained in Eq. (5.25) since the surface potential has been augmented by V(y). It should also be realized that this is a non-equilibrium condition, meaning that the quasi-Fermi level is no longer constant along the channel as shown in Figure 5.6 (d).

Eq. (5.41) cannot be used to determine the drain current since Pap is now a function of y. Under these conditions,

If we use Eq. (5.43) and realize that fey) = -8V(y)/8y, then Eq. (5.46) becomes:

(5.47)

At this point it is important to notice that ID is indeed constant along y. The inversion layer is functioning as a nonlinear resistor so that there is no mechanism to "lose" or "gain" current. To obtain an expression for ID without specifically knowing V(y) we can integrate Eq. (5.47) over y. If we choose y = 0 and y = L as the two end-points, the potentials at these points are known. So

J1.P wear ~V(L)=VDS{VGS - (V(y) + 24>Fn)

V(O)=O

(5.48)

The result of this integration is

ID =

(5.49)

and the current direction is from the drain to source. In both cases, we have taken Vs = VB = 0 in integration.

The first term in the curl-brackets in the above two expressions represents the contribution coming from the oxide capacitor charge (average surface potential in the channel is 2¢>F + VDs!2 where ¢>F is either ¢>Fn or ¢>Fp), and the second term in the curl-brackets is the amount that the current is decreased due to the increase of bulk charge. It is often useful to consider the device operating in a configuration other than with the source and bulk at ground. For this case we can again integrate Eq. (5.47), however we take the substrate rather than source as the reference. This means that along y- axis YeO) = VSB and VeL) = VDB, and VGS in expression of Psp should be replaced by VGB. Thus the integration is proceeded as follows.

5.4. THRESHOLD VOLTAGE IN NONUNIFORM SUBSTRATE 217

VDS, this condition is easily satisfied. Hence for small values of VDS the MOSFET does behave as if the channel is a variable conductance controlled by the gate voltage.

5.4Computation of Threshold Voltage for Nonuniformly Doped Substrate

From the discussion so far in this chapter, we have seen that the threshold voltage, VT, is a critical parameter in determining MOS device characteristics. The derivation of VT in section 5.2, Eqs. (5.36-5.37), is based on the uniformly doped substrate and the criterion for MOS device to be "on" is that the concentration of the minority carriers in the surface inversion layer equals that of the majority carriers in the substrate. Besides, the effect of body bias, i.e., the bias applied to the substrate contact with reference to the source, on the threshold voltage has not been addressed. In practical MOS structures, however, the surface region of the substrate often undergoes channel implantation to have its threshold voltage adjusted to the designed value. Moreover, in the CMOS process, one type of MOS device is actually built in the wells which are formed by the counter-doping of the substrate. This means that the assumption of the uniform doping is usually not valid. With process/device simulation programs SUPREM and SEDAN/PISCES, we should be able to compute the threshold voltage for any general structure. But the definition for "onset" of MOS devices used in the simulation is often different from that defined previously. In fact, during simulation we plot a curve of channel mobile charge (per unit surface area) vs. VGS for a given VSB. Above a certain gate bias, this curve becomes linear, and the intercept at the Vas axis of the extrapolated line of this linear part is taken as the threshold voltage. This simulation approach resembles the practical measurement setup, in which the drain current at the low drain-source bias is used to compute the channel conductance, which is in turn directly related to the channel mobile charge. So even though in device simulation we have direct access to the surface minority carrier concentration, hence in principle we can adopt the criterion for threshold voltage used in section 5.2, in practice we still prefer to use the method outlined above.

In this section and the section that follows, we will discuss the general definition for the threshold voltage in different MOS structures. Af-

ter theoretical derivation of the formulation for computing the threshold voltage, design consideration of MOS devices will be given.

We now address three issues in extending the concept of threshold voltage in a general situation: 1) to handle the nonuniformly doped substrate; 2) to modify the criterion for MOS "on" state; and 3) to explicitly include the effect of VSB in the formulation of threshold voltage

VT.

We start the discussion from a general band diagram for MOS structure. Because the band discontinuity around the oxide layer, we choose the vacuum potential level as the representation of the electrostatic potential. The advantage of choosing the vacuum level to represent potential is that it is always continuous no matter how many different materials there are in the system. There are two particular band diagrams which are of special interest to the clarification of various quantities used in threshold voltage definition. One is the thermal equilibrium at which the Fermi-level of the MOS structure is aligned. Then the potential difference at this state between the gate and any position in the substrate is the reflection of their work function difference. Note that because of the nonuniformity of the doping, the work function is no longer unique in the substrate. Take the substrate contact as the potential reference, the gate potential at the thermal equilibrium is

where <P Msisub refers to the work function difference between the "metal" gate and the semiconductor bulk next to the substrate contact. The other band diagram which has special interest is that at the Hatband condition. Again, because of the doping nonuniformity, there is no truly flat band state. All we are referring to is actually a situation where the overall charge state of the substrate is neutral, or equivalently to say that the electric field at the surface of the substrate (Le., at Si02 /Si interface) is zero. In this flat band condition, the potential at the surface of the substrate is not zero unless the substrate is uniformly doped. We refer this surface potential as 4>sF with F for Hatband. The voltage (not the potential) drop across the gate and the substrate contact at any gate bias can be expressed as