Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

(a)

N

(b)

Figure 5.1: The MOS(FET) (a) section view to illustrate pn junctions and MOS capacitor, (b) a plan view.

centration of ionized donors. This picture is identical to that for the pn junction as depicted in Figures 4.4 (b) and 4.5 (b) (the left half of these figures only).

Again, as for the pn junction, we assume "complete depletion" of electrons (by comparison to the ND concentration). This allows us to find the dependence of electrostatic potential (relative to ground potential) as a function of x. We know that the potential and electric field are both zero for x > Xd. Using the Poisson's equation, one obtains the following relationship.

Hence, the potential, at any point x < Xd, is negative with value given by the above equation. The resulting negative potential is consistent with the fact that we applied a negative gate bias to achieve this band configuration. Note also that as the conduction band energy increases

• x

Figure 5.2: The energy band diagram of the MOS and definition of key terms.

(bends upward), potential decreases.

At x = 0 define the surface potential, <l>s, as:

(5.2)

Unfortunately, we know neither Xd nor <l>s at this point. What is needed is to relate these quantities to known parameters such as the applied voltage. Fortunately we conserve both charge and voltage which provide the needed relationships. First, the applied voltage must equal the potential drop in the semiconductor and across the oxide if at the zero bias (equilibrium) bands in both Si02 and Si are flat:

(5.3)

Second, the net charge in the semiconductor must balance the net charge on the gate, i.e.,

(5.4)

where the poxide capacitance er unit surface area, Cox, is

situation where the value of surface potential leads to the invalidation of assumption p ~ ND.

Clearly, if p = ND we now have to consider the effect of free holes at the surface. Another way to state this is to say that if the hole concentration at the surface equals the electron concentration in the bulk (which is approximately equal to ND) then we have inverted the carrier type at the surface. Using Eqs. (5.16) and (5.17) to show this, for the case of inversion that p(O) = n(xd), one has

From this equation we can solve for 'I/!(O), which is also the <Ps at the

where the last part of the equation results from using Eq. (5.15). Two things can be observed. First, the condition of <Ps = 2<PFn is useful to determine the onset of inversion. Second, physically one can see from the band diagram that one must move the Ei level at the surface as much above EF as it is below EF in the bulk (or vice versa for the n-channel case).

Once this surface inversion has occurred, further negative increases in gate bias can accumulate more free holes at the surface, rather than having to deplete electrons in the bulk at Xd. Thus Xd reaches a maximum when the surface becomes inverted so that using Eq. (5.2):

(remember that <PFn has negative value) and for the n-channel case

Xdmax =

4Again, for the n-channel case this becomes 1/>. = 21/>Fp = 2k; In!:f:t-

As the bias becomes even more negative, we now assume that since Xd does not increase, the surface potential remains constant at 2tPFn. Further accumulation of charge on the metal "gate" occurs, which is now "balanced" by a sheet charge of holes.

(5.26)

and for the n-channel device, the sheet charge of electrons is

The term V-4qf.sND<PFn in the above equations is actually the "bulk" charge, QB (which should more precisely be labeled as QB(2tPFn)). In general, we can say

(5.27)

for p-channel devices and

for n-channel device. Using this notation, Eq. (5.26) simplifies to:

(5.28)

This equation can also be applied to n-channel devices with tPFn replaced by tPFp.

The importance of Eq. (5.28) can be seen most clearly by defining a threshold voltage for inversion. That is:

(5.29)

It should be noted, however, that the above equation is valid only when VG < VTF (Le. !VGI > !VTFI) for p-channel devices.

To this point we have assumed that the contact to the n-region occurs only at the back of the substrate. If, on the other hand, a p-type contact is available to the surface of the substrate as well as the back contact then the surface inversion charge can respond at higher frequencies since holes can be provided and extracted via this contact. Such a case occurs for the MOS with p-contact as is shown in Figure 5.1 (a). If one were to "short" the back n-contact and one (or both) p-contact to each other, the observed C(V) vs. V characteristic would be that of the low frequency curve (Le., device response time is short compared to the period of the external signal change).

So far, our discussion has been based on the assumption that for V = 0 the energy bands in semiconductor and in oxide are flat. This is the reason why there appears a F in above definition of the threshold voltage, VTF. However, this is typically not the case. There are two major causes for deviations of the band diagram from the "flat band" condition: 1) the work function difference between metal (or gate material) and semiconductor and 2) fixed charge present in the oxide due to the fabrication process. The work function difference is related to the potential needed to adjust for difference in the highest available energy states for electrons. Taken as reference the vacuum level, for a metal, this energy is called the work function q,M. For the semiconductor the energy difference between the conduction band and the vacuum level is the electron affinity, XS. And the semiconductor work function, q, s, is determined by both the electron affinity and energy difference between the Fermi level and conduction band, which is affected by the carrier population, hence related to the impurity doping level. Thus for the case of silicon gate technology, the work function on the gate also depends on the doping. Figure 5.3 (a) shows the case of an n+ gate with p-type

-

Figure 5.3: Various Hatband conditions for polysilicon gate MOSFETs.

(a) n+ gate, n-channel, (b) n+ gate, p-channel, (c) p+ gate, p-channel.

substrate (Le., n-channel device). Here the band line-up is shown and since both gate and semiconductor have the same xs contributing to the work function, the difference 9?MS is just the difference in Fermi level in the two materials. Assuming that for the heavily-doped n+ -gate,

EF = Ee:

9? MS = xs - [XS + ( ~g + kT In ~:) ]

the gate-material- semiconductor work function difference is -0.88 eV. Again considering the case of n+ gate but using the n-type substrate (Le., p-channel devices), Figure 5.3 (b) shows the appropriate flatband

band diagram. Here, the Fermi level is much closer to the conduction band so that in fact

Again assuming a doping level of 5 x 1015 cm-3 , the work function difference is -0.22eV. As we will see in the discussion of the technology dependence for MOSFET threshold voltages, this asymmetry for iflMS values can cause some difficulties in matching thresholds voltages and also in maintaining reasonable doping levels. Hence, as a final example, Figure 5.3 (c) shows the case of a p+ doped gate for the case of n-type substrate. Now on the gate side EF = Ev and the resulting work function difference is

iflMS = (xs+Eg)-[xs+(~g-kTln:~)]

If we consider the actual numbers as given above, we'll find that the work function difference is +0.88 eV. Notice that this is now exactly the dual situation of that shown in Figure 5.3 (a). This has very desirable properties from the point of view of engineering the substrate doping levels. Unfortunately, it poses some important technology difficulties which only recently have been overcome.

Having considered the conditions for flat band imposed by the socalled "metal" - semiconductor work function difference, let us consider the second contribution to the flat band voltage shift. During fabrication, the gate oxidation process consumes silicon to produce Si02. During this process, excess silicon, not needed in the less dense Si0 2 is generated and moves both into the oxide and into the silicon bulle The excess silicon in the bulk becomes the interstitials which affect diffusion (OED) while most of the silicon in the oxide is consumed subsequently in further oxidation. However, it is thought that excess silicon remaining near the interface - either free or partially-bonded to the substratetakes on a positive charge state at room temperature. This charge is the so-called fixed charge Qf. Since it resides at the Si02/Si interface it can be thought of as stored charge on one plate of the gate-oxide capacitor.