Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

Figure 4.30: SEDAN output of electrostatic electron and hole quasiFermi potentials versus depth (n+p diode, V = 0.9V).

region, whereas the same two components for holes tend to balance each other. From the above analysis, we can make a bold assumption that in this region, the hole current can be considered negligible, i.e., roughly being zero. This assumption seems to violate the common sense that the total current in a neutral region consists mainly of the majority current component. But keep in mind that our discussion is limited in the region where n ~ p, i.e. the quasi-neutral region, not the actual neutral region where n i- p. Nonetheless, we will let the subsequent computation justify whether the assumption made is reasonable.

Assuming that Jp ~ 0,

where 6.x is in units of /-Lm and kT/ q has units of V. Based on this field distribution and the carrier distribution for electrons we can compute the drift component at any position, say 6.x = 0.7 /-Lm, Le. x = 1.0/-Lm, as

Jndriftb:z:=O.1 = q/-Lnn£I~:z:=O.1

=-q x 1.36 X 103 x 2.01 X 1011 x 2.55 X 102

whereas from Figure 4.29 the total electron current density is 2.34 x 104 A/cm2 • The above drift component accounts for roughly half of the entire electron current at this point. The analytically calculated value of the electric field is £(x = 1.0 /-Lm) = 259V/ cm, whereas SEDAN gives value of 254V/cm (an error of +1.6%). Similarly the calculated electron density is n(x = 1.0 /-Lm) = 2.06 x 1011 cm-3 , whereas the SEDAN value is 2.13 x 1011 cm-3 (an error of -3.3%). Clearly these numbers and errors are quite acceptable, given the very rough approximation made. Moreover, one can integrate £(6.x) to check the potential drop across this quasi-neutral region:

Note that in the derivation of the second expression above, Eq. (4.120) is used for the expression of £ and an assumption has been made that the point where the electron distribution crosses the doping level of the substrate, Le., n = p = Ppo, is used as the ending point in the integration. 6.1jJ thus calculated is 133 mV. Compared to the simulation result of 140 mV from SEDAN (Figure 4.30), there is only 7 mV discrepancy, which is caused by the fact that the assumption of n ~ p breaks down in the vicinity of the substrate contact, where the effect of the ionized doping concentration cannot be neglected. In fact the simulation shows that in the proximity of the contact, there exists a negatively charged region due to the excess of combined population of electrons and ionized acceptors over that of holes. In a very short distance (about 60 Afrom the contact), there is an additional voltage drop of about 7 mV.

190 CHAPTER 4. PN JUNCTIONS

The above discussion confirms that the assumption of n ~ p in the p-substrate under high-level injection can be used to predict the device behavior very well except at the last few tens of angstroms from the contact. Also note that the above discussion is based on the short-base assumption, i.e. the width of the lightly-doped layer is small compared to the diffusion length of the injected minority carriers.

As the last part of this section, let us check the portion of the applied voltage which drops across the p-region for this particular bias. It should be noted that the voltage drop is not essentially the same as the potential drop, which is measured by the potential difference at any two given points. Usually, the voltage drop can be measured by the difference of the Fermi potential (</» for the majority carriers. In the case of the current example (Figure 4.30), voltage drop over the p-region if measured by the difference of </>p is 8 mV, whereas the potential drop is 140 mV as cited before. The discrepancy between voltage and potential drops is caused by the built-in potential at the equilibrium. Again, we can check the total bias (0.9 V) against the sum of the analytically-obtained voltage drop across the physical junction from Eq. (4.117) (0.888 V) and the simulation-derived value of voltage drop over the p-region (0.008 V). The error is extremely small (about -0.7%), which further confirms the applicability of Eq. (4.117) at the high-level injection.

In summary for this section, we have taken an n+p junction device and looked at both solutions for the Poisson's and continuity equations at the different bias conditions. The Poisson's solution shows some of the results predicted by the ideal theory as well as some rather unusual results - partly due to nonuniform doping levels and partly due to charge spill-over into the neutral capacitance region of the device. Looking at the current continuity results, we have explored several features of the dynamic current range of the n+p junction. Of particular interest is the trade-off in recombination terms between space-charge and other regions of the device at low bias levels. For high current levels we see a non-ideal slope due to both ohmic voltage drops and extra bias needed to sustain the high-level injection boundary condition. In the next section we turn to some device implications of the technology dependence of the diode behavior.

192 CHAPTER 4. PN JUNCTIONS

21,-----------------------------~

c:17

Figure 4.32: Reduced n+ concentration compared to an LDD-like structure.

The basic I - V characteristics of the structures shown in Figures 4.31-4.32 generally follow the abrupt n+p diode characteristics outlined in Section 4.7.2. Recombination in the space-charge region and in the n+ (emitter) region, however, show the strongest deviations.

Although the added profile has little effect in the n+ region it definitely alters the space charge recombination parameters. In fact, as we will see later for the bipolar transistor, as the p-type doping is increased still further, the space-charge term is altered dramatically. This result suggests that for an improved diode leakage characteristics, there is a trade-off to be made - for higher boron doping levels the recombination initially decreases while the space-charge capacitance increases. For virtually all circuit applications this change in capacitance is an undesirable effect since larger capacitance is detrimental to circuit speed. Many MOS structures are being "engineered" this way in the drain region to reduce electric fields. These structures are referred to as LDD devices as mentioned previously. Primarily the LDD is used to control and reduce lateral electric fields at the drain because such fields adversely affect hot-carrier performance [4.14].

The conclusion from the above example is that one can dramatically

alter the dependence of recombination in the n+p junction by altering doping profiles. Doping profile changes can be used to reduce the impact of many of the factors that contribute strongly to junction recombination/generation. For example, the LDD structure can potentially have a very positive impact on junction recombination parameters.

4.8Summary

In this chapter we have considered both the analytic solutions to the pn junction diode as well as numerical solutions using the SEDAN program. The analytic solutions have great elegance in providing key device insight, however they require a substantial number of assumptions in their derivation. The use of SEDAN (and PISCES) has been invaluable in seeing the complete device results and thereby making it easier to see the role of the analytic solutions. Moreover, there are details such as the high-level injection and technology dependence of generation/recombination that are intractable problems without some form of numerical solution. In these cases SEDAN and PISCES allows us to view the physical results directly. In subsequent chapters we will use this same approach to consider both the MOSFET device and finally the bipolar junction transistor.

4.9Exercises

4-1 Construct an ideal np junction with ND = 1016 cm -3 for 0 < x < 2 [tm and NA = 1015 cm-3 for 2 [tm < x < 10 [tm. Set 'To = 5 X 10-9 sec so that the long-base diode solutions can be observed. Compute SEDAN or PISCES solutions for V =0 and V =0.57 V forward bias.

1.Extract In and Ip and compare with the analytical equations.

2.Calculate Lp in the n-region and Ln in the p-region and determine whether the longor short-base solutions apply.

3. For V = 0.5 V extract Jp in the n-region and I n in the p-region at the space-charge edge and compare with the appropriate equations.

4.Repeat step 3 for the default 'To and comment on the observed differences.

0.9V.

1.Compare the slope with the "ideal" and 2kT/q values.

2.Estimate the voltage where the high-level injection begins.

3.Use Eq. (4.117) to compare with your result in step 2 and discuss.

4-3 Use Figure 4.24 and Eq. (4.96) to extract Jo for a bias of V = 0.5 V.

4-4 For the point x = 0.324 pm in the example given in Section 4.7.2, compute the drift and diffusion components of current for both holes and electrons (be careful about signs). Compare these values with those given in Figure 4.29.

4-5 For the p+n diode created by the n-well and p+ source/drain contacts (see Chapter 1), analyze the following:

1. Plot u(x) vs. x for V = 0.5 V.

2. Decrease the lifetime by a factor of 3 and repeat step 1.

4.10References

[4.1] Z. Yu and R. W. Dutton, "SEDAN III-A generalized electronic material device analysis program," Stanford University Electronics Laboratories Technical Report, July 1985.

[4.2] C. D. Thurmond, "The standard thermodynamic fraction of the formulation of electrons and holes in Ge, Si, GaAs, and GaP," J.

Electrochem Soc., 122, p. 1133, 1975.

[4.3] C. Kittel, Introduction to Solid State Physics, John Wiley, NY, 1986

[4.4] C. Kittel and H. Kroemer, Thermal Physics, 2nd edition, W. H. Freeman & Co., San Francisco, 1980.

[4.5] J. S. Blakemore, Semiconductor Statistics, Dover Pub., Inc., New York, 1987.

Chapter 5

MOS Structures

5.1Introduction

The previous chapter discussed the analysis of pn junctions using both analytical and numerical techniques. The pn junction is an essential component in all aspects of silicon IC's. In bipolar technology, it forms the active source for injecting carriers and the collecting junction to extract them. In Chapter 6 we will return to the discussion of these bipolar applications. For MOS technology the pn junction is an essential "parasitic" component. Namely, the source and drain junctions are indeed diodes but their main purpose is to form lateral majority-carrier sources and sinks to a gate-induced inversion layer (inverted with respect to the substrate which is in the opposite carrier type from the source and drain). In this chapter we will analyze the MOS gate structure in conjunction with our previous analysis of the pn junction in order to study the MOSFET. Specifically, we will build upon the Poisson's solutions from Chapter 4 and introduce the additional concepts needed to understand inversion layers in the MOS device. By adding the actual source and drain regions in the form of pn junctions, we will create and analyze the MOSFET. Based on the approach used in Chapter 4, we will first develop the analytic models. Subsequently, we will use SEDANIPISCES to explore and develop a deeper understanding of the analytic results. A range of technology dependencies can be understood and quantified where the first-principle analytic models break down.

The organization of this chapter is as follows. Section 5.2 considers the MOS device as a capacitor, and defines the notion of threshold

voltage. Section 5.3 extends the MOS consideration to the effects of lateral charge motion in the channel and expressions for the drain current are given. In Section 5.4 the threshold voltage is redefined for a more general situation - either enhancement or depletion MOS with nonuniformly-doped substrate - and its computation through numerical simulation is discussed. In Section 5.5 we use SUPREM and SEDAN to explore many of the non-ideal effects in the MOSFET. In particular, nonuniform channel doping in both n- and p-channel devices is considered. In addition, effects such as subthreshold, special capacitance, and large vertical field effects are introduced. Finally Section 5.6 gives a brief summary of this chapter.

5.2The MOS Capacitor

The MOS capacitor conventionally consists of a "metal" layer which is deposited on an oxide-semiconductor pair. For silicon technology, the surface oxide layer, Si02 , is grown by heating the silicon in an oxygen ambient as discussed in Chapter 2. The MOS capacitor, like the pn junction, is a building block which is used to construct more complex semiconductor devices. Figure 5.1 (a) is the cross-sectional view of a MOS field-effect transistor (MOSFET) and Figure 5.1 (b) shows a plan view of this device. Notice, with the aid of the dashed lines in Figure 5.1 (a), that the MOSFET structure incorporates both pn junctions and the MOS capacitor structure. By considering the operation of the MOS capacitor, with the previous results for the pn junction, we have the ground work necessary to discuss the MOSFET structure.

To begin the discussion of the MOS capacitor, consider the energy band diagram for the Section AA shown in Figure 5.1 (a).

It is useful to consider the band diagram under bias to discuss the dependence of the potential drop in the semiconductor on the applied "gate" voltage and also to determine the physical limits of the spacecharge region, Figure 5.2 shows the band diagram resulting from a negative bias applied to the metal gate. Assume that the potential at the contact to the n-type substrate is taken zero (grounded), x = 0 at the Si02 /Si interface, and x = Xd when the space-charge region ends. As one moves toward x = 0 from x > 0 the conduction band edge moves away from the Fermi-energy level, hence decreasing the free electron concentration by orders of magnitude and exposing the constant con-