Книги2 / 1993 Dutton , Yu -Technology CAD_Computer Simulation

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for technology (TCAD) - tools for process analysis and device design. In particular, at Stanford we have developed the SUPREM (process modeling), SEDAN and PISCES (device analysis) programs that make it easy for the user to simulate technology and device effects - these tools are as easy to use as SPICE. Hence, the key focus of this text is to introduce the use of these TCAD tools in the context of design of MOS and bipolar devices. In fact, we take a real CMOS process, developed in our Stanford IC Laboratory, and use all aspects of the technology cross-sections to illustrate the use of TCAD in process/device analysis and design. To get a quick glimpse of how this approach differs from other device texts, scan the text and see the numerous outputs from SUPREM, SEDAN and PISCES which almost always show the trade-offs between simple analytical models and the realities of dealing with practical devices. Of equal, and maybe greater, importance is the fact that these simulations are immediately available to the teacher and student to re-run and hence explore the multi-dimensional space of physics and device design. While the text was originally written using one-dimensional versions of TCAD tools, the application of TCAD in both industry and in academia has shifted strongly to the 2D domain. Hence, Appendix C has been added to this first edition that provides "templates" so that the user can reproduce all the device analysis experiments using either SEDAN or PISCES. Moreover, for those interested readers, we are happy to provide all our templates electronically (e-mail) upon request. Please send such requests to "dutton@sierra.stanford.edu."

Another key issue is where this text fits in a device/process physics curricula and how to approach the teaching of such a course. In most undergraduate EE and virtually all graduate programs there are courses on device physics and processing technology (frequently as one single course). This text has a very strong connection to the material covered in the device modeling area and a supplemental connection to material in the typical processing technology course. Given a reasonable junior level device/process course, this text provides the opportunity to initiate a project course that allows the students to do directed work in both experimenting with physics they've learned and in going beyond the simple first-order formulations. Moreover, there is a unique opportunity for students to embark on real device/technology design and independent study. In the case of MS/Ph. D. graduate programs such as the one we have at Stanford, this text and course material provides the foundation for research in both advanced device design and manufacturing science.

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In fact, we now consider the use of these TCAD tools to be strategic in the sense that their use is being integrated directly into core courses on process and device physics. I expect that in industry as well, this approach can be especially effective in providing a hands-on training experience. In the case of graduate and industrial environments, the final chapter of the book takes the CMOS process example, used throughout the book, and shows the process of transformation into a BiCMOS process. In the Stanford course, we have the students modify and redesign the process to meet electrical performance specifications for both the MOS and bipolar devices.

In closing, we would like to open the door for a dialog with those of you in either academia or industry in considering how to make this hands-on (and open-classroom) approach be effective in your environment. The software (SUPREM, SEDAN and PISCES) as well as all simulator inputs shown in the text are available. Moreover, we are trying to develop other instructional material such as on-line lecture notes and project examples to illustrate how to bridge gaps between the worlds of problem-sets, research, development, and manufacturing.

Robert W. Dutton

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The material used in this textbook and associated course materials prepared by Stanford University for both regular and short courses fit into the mission of NCCE to promote broad dissemination and use of technology computer-aided design (TCAD) tools both in industry and academia. The National Center for Computational Electronics (NCCE) was established through a National Science Foundation (NSF) grant to the University of

Illinois. In 1992, the Center was renewed and Stanford University joined Illinois as a co-hosting institution. The mission of NCCE is to facilitate collaborative research in the area of computational electronics-the broad area of semi-conductor modeling ranging from first-principles physical models through compact (analytical) models used for circuit design. NCCE helps to organize and to host technical meetings, workshops, and short courses that promote both research and education in computational electronics.

TECHNOLOGY CAD-COMPUTER SIMULATION OF IC PROCESSES AND DEVICES is a new approach to teaching the analysis and design of integrated circuit devices and technology. For the first time this text brings together the use of simulation tools with the more traditional analytical solutions to process and device physics. Industry-standard simulators such as SUPREM for process modeling and PISCES for device analysis are used to give students hands-on access to examples that go beyond simplified assumptions such as uniformly doped channels (MOS) and abrupt junctions (diodes and bipolar transistors). Moreover, the coupled use of SUPREM and PISCES make it possible to explore interactions of process and device effects-for example, the role of implantation dose and range on MOS threshold voltage and bipolar current gain. In addition to the systematic evaluation of device effects based on the use of TCAD simulation, the text offers an opportunity to ~ook at the issues of process integration and the trade-offs of merged BiCMOS technology. The text provides not only details of the 1.5 Jlm BiCMOS process used at Stanford University in its research program but examples that reflect industrial BiCMOS over three generations of technology development.

TECHNOLOGY CAD

--

COMPUTER SIMUlATION

OF IC PROCESSES

AND DEVICES

Chapter 1

Technology-Oriented CAD

1.1Introduction

The rapid evolution and explosive growth of integrated circuit technology have impacted society more than any other technological development of the 20th century. Integrated circuits (ICs) are used universally, in everything from computer technology, communications, and information processing to transportation, residential and recreational applications. In fact, it is becoming difficult to find applications in which IC electronics have not been used. The expanding use of IC technology requires more accurate circuit analysis methods and tools, prompting the introduction of computers into the design process. The goal of this book is to build a firm foundation in the use of Computer-Assisted techniques for IC device and process Design (CAD). Both practical and analytical viewpoints are stressed to give the reader the background necessary to appreciate CAD tools and to feel comfortable with their use.

1.1.1 Ie Technology Development

This section presents the evolution of CAD as a field of specialty and explains why it is useful, in fact critical, for IC development.

In the ten years after the invention of the bipolar transistor in 1947, circuit design and production were accomplished largely by placing discrete components on printed circuit boards. By late 1950s, complete circuits including both active and passive devices were realized on monolithic silicon substrates. Important new considerations emerged, such as the impedance of local interconnections and the interaction of devices

with the silicon substrate and with other devices. Computer simulation evolved as a practical way to predict circuit performance, including nonlinearities, because digital computers were capable of complex circuit analysis based on a network, or matrix, formulation. By the 1970s, the circuit simulator had progressed from a useful design tool to a critical one, essentially replacing the breadboarding of prototypes. The SPICE program, or "Simulation Program with Integrated Circuit Emphasis," developed at the University of California, Berkeley, became a household word among the entire circuit design community [1.1].

Meanwhile, the IC industry had reached an important juncture in its development. While the 1950s and 1960s were dominated by bipolar transistor technology, the 1970s saw Metal-Oxide-Silicon (MOS) technology begin to overtake bipolar technology in terms of functional complexity and level of integration. MOS technology set forth on a path of geometrical scaling to escalate chip complexity and to challenge bipolar circuits in the area of high speed applications. Complementary MOS (CMOS) technology, with its solid entry as a cost-effective technology solution in the 1980s, began to replace bipolar technologies such as TTL along some system application paths. In these cases, TTL became system interconnection "glue circuitry" rather than cutting-edge performance technology.

With aggressive efforts to scale MOS devices in the mid-1970s, transistor dimensions soon reached the point at which first-order assumptions about physical effects and dopant distributions began to break down. Specifically, MOS devices were going to channel lengths below 10 f.Lm while source/drain junction depths remained in the range of 1 f.Lm, so junction depths were a significant fraction of the channel dimension. The introduction of silicon gate technology allowed gate dimensions to be scaled down even farther, but without shallower junctions, channel lengths below 2 f.Lm were very difficult to model. For the MOS, the intrinsic device problems such as output conductance, velocity saturation, and subthreshold behavior all received substantial interest and effort. Two-dimensional computer tools were used extensively to study these effects.

By the mid-1970s, the critical role of processing technology in establishing device characteristics was evident. Many important interrelated process and device effects were identified by means of computer coupled analysis tools. Industrial leaders such as IBM and Texas Instruments had aggressive efforts to model process physics and to relate these mod-

els to device characteristics and circuit statistics. A unified process and device simulator, the SITCAP program (SImulator for Transistors to CAlculate Parameters) was developed at Katholieke University, Leuven, Belgium [1.2]. This program inputs process specifications (processing times and temperatures) along with simple mask geometries, and outputs I-V and C-V curves, along with selected SPICE model parameters. Based on several years of experience with SITCAP, the Stanford research group undertook the task of developing a more complete process simulation program, building on ideas obtained from SITCAP, SPICE and CASPER (Computer-Aided SEmiconductor Processing analysis including Epitaxial Redistribution), a process analysis program developed jointly at Lehigh University and Bell Laboratories [1.3]. Stanford University developed the SUPREM program (Stanford University PRocess Engineering Models) and released the first version in 1977 [1.4]. Since then, the process models in SUP REM have developed substantially and will continue to evolve due to ongoing efforts at Stanford and in industrial and other research laboratories world-wide. Versions II and III of SUPREM were released in 1978 [1.5] and 1984 [1.6], respectively. Now, from a technology perspective, we see a fairly even match between MOS and bipolar technologies. High speed RAMs and CPUs continue to use bipolar, while high-density memories and large systems chips are dominated by MOS. In addition, new technologies have emerged. In particular, gallium arsenide (GaAs) technology has developed to the point where it is competing strongly with bipolar devices for the high- speed/low-power market. SPICE has long been recognized as the preeminent circuit analysis CAD tool, but as scaling pushes IC devices up against technological limits there is strong motivation for the use of both process and device CAD as well. The development and broad acceptance of the SUPREM program indicates that process CAD has become a vital force in IC technology development.

1.1.2Overview of Subsequent Chapters

This book presents a unified discourse on process and device CAD as interrelated subjects, building on a wide range of experiences and applications of the SUPREM program. Chapter 1 focuses on the motivation for coupled process and device CAD. Specific applications are presented and the Stanford CMOS technology is introduced as an example for detailed discussion. Subsequent chapters use this Stanford

4 CHAPTER 1. TECHNOLOGY-ORIENTED CAD

technology to develop process and device CAD examples. In Chapter 2, SUPREM III is introduced, and process CAD is discussed in terms of ion-implantation, impurity diffusion, and oxidation models. Chapter 3 introduces the Stanford device analysis program SEDAN III (SEmiconductor Device ANalysis) [1.7]. The use of SEDAN III to analyze MOS field-effect and bipolar devices is demonstrated. Even though for the nature of the problems discussed in that chapter, the one-dimensional (lD) device simulator is sufficient, in view of the wide availability of PISCES, a two-dimensional (2D) device simulator, we have included several "template" files in Appendix C to help translate these ID problems to 2D input files for PISCES to simulate. The next three chapters move into greater detail concerning device operating principles and analysis techniques. Chapter 4 reviews the classical formulation of pn junction theory and uses device analysis (SEDAN) both to evaluate some of the classical assumptions and to investigate the difficult problem of high level injection. Chapter 5 returns to MOS devices, reviews the first-order MOS theory, and introduces some important second-order effects. Several device analysis examples are introduced in which process technology dramatically affects threshold variations-with substrate bias and as a function of various technology changes. Chapter 6 considers the bipolar transistor. The technology-oriented effects which are represented by physical models such as the charge-control model (Gummel-Poon (GP)formulation) [1.8] are discussed. The technology dependence of parameters such as concentration dependent carrier lifetime and emitter recombination are illustrated using device analysis. Finally, Chapter 7 considers the application of process simulation and device analysis to technology design. The BiCMOS process is selected as a useful design vehicle for two reasons. First, it allows the reader to pull together concepts from the entire book. Second, the inherent nature of BiCMOS technology offers real constraints and hence trade-offs which must be understood and accounted for. Three appendices are included at the end of the book. Appendix A gives a brief introduction to the numerical methods used in both process and device simulation, and issues peculiar to the device simulation are discussed in length. Appendix B describes step-by-step the Stanford 2 J-Lm BiCMOS process and its design consideration. Finally Appendix C provides PISCES input files for both BJT and MOS capacitor simulation.

1.2Process and Device CAD

1.2.1Introduction

Computer-assisted design tools are still evolving, so the nature of how the tools are used depends strongly on what tools are available. The hist.ory of process and device CAD is closely linked to the development of efficient computers and reliable mathematical models. For example, during the 1960s and 1970s, CAD tools were sufficient to extract currentvoltage characteristics but were not frequently used for transient device analysis. Due to recent advances in computer technology, transient analysis is now cost-effective, and simulators can embed device-level structures in circuit models. Transient device simulations are used to analyze problems such as CMOS latch-up and memory cell upset due to transient radiation. In the area of process simulation, physical models for process technology were rather limited in the 1960's and 1970's. In addition, device dimensions were not small enough to justify sophisticated process simulators with two-dimensional models. Now, the physical understanding of processes has advanced significantly; moreover, the current evolution into the submicron device dimensions regime necessitates accurate process models in two dimensions [1.9].

The following discussion uses many examples, both historic and state-of-the-art, to illustrate the development of device and process CAD. For the most part, the roles of process and device CAD are discussed as separate entities. It should become apparent, however, that the two are synergistically linked. An understanding of the various fabrication steps is crucial to predicting device performance. In fact, the underlying physical process variations control the observed electrical variations.

1.2.2History of Device CAD

The use of CAD for IC device analysis dates nearly to the invention of the transistor. Once the operating principles of any device have been experimentally demonstrated, designers - especially circuit and device designers - want to optimize the device's performance for specific applications. This optimization is not a simple task, particularly if the equations describing device operation are complex. In the case of semiconductor devices, particle conservation is described by several cross-coupled non-linear partial differential equations. The Poisson's

6 CHAPTER 1. TECHNOLOGY-ORIENTED CAD

equation describes the interaction of charged particles due to electric fields, and the continuity equations describe particle concentrations as they relate to particle fluxes, generation, and recombination. Electron and hole concentrations are exponentially related to potentials through Boltzmann, Fermi-Dirac, or other exponentially-determined probability distribution functions. These device equations are cumbersome to work with by hand, making computer-aided analysis a desirable alternative.

Our first example of CAD for IC technology is in the analysis of bipolar devices. The Ebers-Moll (EM) circuit model [1.10] provides an excellent framework to describe all three modes of bipolar circuit behavior (dc, ac, and transient). However, in order for the EM model to be useful in practice, reliable values for the model's parameters must be generated. CAD tools are useful for linking fabrication conditions to EM parameters. For example, the device simulator uses inputs such as device geometry, doping profile, and bias conditions to generate data files for characteristics such as capacitance and current vs. voltage. The simulated data files are then used to extract EM or Gummel-Poon (GP) model parameters (Figure 1.1).

For MOS devices, CAD became important in the mid-1970s when MOS technology emerged as a viable means to create high density ICs. Two factors contributed to this successful evolution. First, sources of problematic threshold voltage shifts were identified and brought under control. Such sources include charge in the oxide due to external contamination and traps at the silicon-insulator interface due to the oxide growth process. Second, limitations in threshold voltage tolerance were overcome by the introduction of ion implantation for channel doping. Before ion implantation, variations in substrate doping from wafer to wafer led to variations in threshold voltages, since the channel was not subject to any additional doping. With ion implantation, channel doping profiles became accurate and repeatable. Unfortunately, ion-implanted profiles are also spatially nonlinear, and therefore require more sophisticated, two-dimensional device analysis tools. Thus, as early reliability problems were brought under control, device CAD tools became even more crucial for threshold voltage characterization and optimization.

Figure 1.2 shows the results of 2D simulations of drain current vs. source-drain voltage with a given gate-source voltage. Two similar technologies are compared; one with a lightly doped substrate and ion implanted channel doping, and one with a more highly doped substrate and