Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

grown from a 10 nm pad oxide with a 100 nm nitride layer. The input file for this example is shown in Fig. 2.16. The starting oxide shape is defined by several GRID cards placed between STRUCTURE and END cards. A GRID card allocates node points on a straight segment of the initial oxide surface. The first GRID card assumes that the starting position of the first segment is (0,0). The end position of the segment is given by the two parameters (X.POSIT, Y.POSIT). The distances between two adjacent nodes are determined by the total number of spaces within the segment and the first/last spaces in the same way as in SUPRA. However, to give sufficient flexibility to the segment orientation, two different notations are allowed for the first and last spaces. Either HX1 or HY1, for an example, can be chosen for a segment that is neither exactly in the horizontal nor in the vertical direction. If the segment is only in the horizontal direction, HX1 and HX2 must be used because there is no y-direction change. The boundary condition that the oxide surface is facing is also specified in the GRID card. The present version of SOAP accepts SILICON, NITRIDE, OXYGEN, or REFLECT boundary condition which specifies that the contacting material is a silicon substrate, a nitride layer, oxygen ambient, or oxide bulk with infinite extension, respectively. One should be cautioned that the position specified by the last GRID card is connected to the starting point (0,0) with a reflecting boundary condition.

The following NUMERICAL card is to control the numerical convergence, simulation time step, and orientation effect. The parameter DOX = 0.05 indicates that the incremental oxide thickness between two simulation steps is fixed by 0.05 p.m and therefore the time step is determined by the oxide thickness. When NO.PRESS is specified in the NUMERICAL card, the program is forced to iterate only once in the pressure-velocity iteration algorithm. Although this mode gives an approximate solution that the pressure is constant, fairly close oxide shapes can be obtained with much shorter computation time. Therefore, it is recommended to use this NO.PRESS mode to check the current input file including the definition of the initial structure as well as the final oxide shape expected. The PHYSICAL card allows users to

be able to change such parameters related to their own process conditions as oxide growth rate constants. If a user wants to see intermediate oxide shapes during calculation, he can specify a PLOT.2D card beforehand. The OXIDIZE card is to initiate an oxidation step. The final oxide thickness or the total oxidation time can be specified. The initial oxide thickness should be consistent with the initial oxide structure defined by GRID cards. The simulation result is shown in Fig. 2.17.

References

[2.1] DA. Antoniadis, S. E. Hansen, R. W. Dutton, and A. G. Gonzales, "SUPREM I - A Program for IC Process Modeling and Simulation," SEL 77-006, Stanford Electronics Laboratories, Stanford University, Calif., May 1977.

[2.2] DA. Antoniadis, S. E. Hansen, and R. W. Dutton, "SUPREM II - A Program for IC Process Modeling and Simulation," TR 5019.2, Stanford Electronics Laboratories, Stanford University, Calif., June 1978.

[2.3] C.P. Ho and S. E. Hansen, "SUPREM III - A Program for IC Process Modeling and Simulation," TR SEL 83-001, Stanford Electronics Laboratories, Stanford University, Calif., July 1983.

[2.4] D. Chin, M.R. Kump, and R.W. Dutton, "SUPRA: Stanford University PRocess Analysis Program," Stanford University Laboratories, Stanford University, Stanford, Calif., July 1981.

[2.5] D. Chin, M.R. Kump, H.G. Lee, and R.W. Dutton, "Process Design Using Two-Dimensional Process and Device Simulators," IEEE Trans. on Electron Devices ED-29, Feb. 1982, pp. 336-340.

[2.6] D. Chin and R.W. Dutton, "SOAP: Stanford Oxidation Analysis Program," Stanford University Laboratories, TR SEL 83-002, Stanford University, Stanford, Calif. Aug. 1983.

[2.7] B.R. Penumalli, "A Comprehensive Two-Dimensional VLSI Process Simulation Program - BICEPS", IEEE Trans. on Electron Devices ED36, Sept 1983, pp. 986-992.

[2.8] G.E. Smith, III, and A.J. Steckl, "RECIPE - A Two-Dimensional VLSI Modeling Program," IEEE Trans. on Electron Devices ED-29, Feb 1982, pp. 216-221.

[2.9] KA. Salsburg, and H.H. Hensen, "FEDSS - Finite-Element Diffusion - Simulation System," IEEE Trans. on Electron Devices ED-30, Sept 1983, pp. 1004-1011.

[2.10] J. Linhard, M. Scharff, and H. Schiott, "Range Concepts and Heavy Ion Ranges," K Dan. Vidensk. Selsk., Mat. Fys. Medd., 33(14), 1%3

[2.11] T.M. Liu and W.G. Oldham, "Channeling Effect of Low Energy Boron Implant in <100> Silicon," IEEE Electron Device Letters, EDL-4, Mar. 1983, pp. 59-62.

[2.12] W.K. Hofker, "Implantation of Boron In Silicon," Philips Research Reports Supplements, no. 8 , 1975.

[2.13] M.G. Kendall and A. Stuart, The Advanced Theory of Statistics,

(Charles Griffin, London, 1958).

[2.14] H. Ryssel, G. Prinke, K. Haberger and K. Hoffmann, "Range Parameters of Boron Implanted into Silicon," Appl. Phys., 24, Jan 1981, pp. 3943.

[2.15] M. Simard-Normandin and C.Slaby, "Empirical Modeling of Low Energy Boron Implants in Silicon," 1. Electrochem. Soc., 132, Sept 1985, pp.2218-2223.

[2.16] B.E. Deal and A.S. Grove, "General Relationship for the Thermal Oxidation of Silicon," I. Appl. Phys, 36(12), Dec 1%5, pp. 3770-3778.

[2.17] C.P. Ho, J.D. Plummer, RE. Deal, and J.D. Meindl, "Thermal Oxidation of Heavily Phosphorus Doped Silicon," I. Electrochem. Soc., 125, Apr 1978, pp. 665-671.

[2.18] H.Z. Massoud, "Thermal Oxidation of Silicon in Dry Oxygen - Growth Kinetics and Charge Characterization in the Thin Regime," Stanford Electronics Laboratories, TR G502-1, Stanford University, Stanford, Calif., June 1983.

[2.19] R.B. Fair and J.C.C. Tsai, "A Quantitative Model for the Diffusion of Phosphorus in Silicon and the Emitter Dip Effect," J. Electrochem. Soc., 124, July 1977, pp. 1107-1121.

[2.20] H. Runge, "Distribution of Implanted Ions under Arbitrarily Shaped Mask Regions," Phys. Stat. Sol. (a), 39,1977, pp. 595-599.

[2.21] J. Huang and L. Welliver, "on the Redistribution of Boron in the Diffused Layer during Thermal Oxidation," 1. Electrochem. Soc., 117, 1970, pp. 1577-1580.

[2.22] H.G. Lee, R.W. Dutton, and DA. Antoniadis, "On Redistribution of Boron during Thermal Oxidation of Silicon," J. Electrochem. Soc., 126, 1979, pp. 2001-2007.

[2.23] M.R. Kump and R.W. Dutton, "An Overview of Process Models and Two-Dimensional Analysis Tools," Stanford Electronics Laboratories, TR G-201-13, Stanford University, Stanford, Calif., July 1982.

[2.24] JA. Greenfield and R.W. Dutton, "Nonplanar VLSI Device Analysis the Solution of Poisson's Equation," IEEE Trans. on Electron Devices, ED-27, Aug 1980, pp.1520-1532.

[2.25] R.B. Marcus and T.T. Sheng, "The Thermal Oxidation of Shaped Silicon Surfaces," 1. of Electrochem. Soc., 129, June 1982, pp. 1278-1289.

[2.26] L.O. Wilson, "Numerical Simulation of Gate Oxide Thinning in MOS Devices," 1. Electrochem. Soc., 129, Apr 1982, pp. 831-837.

[2.27] D.Chin, S.Y. Oh, S.M. Hu and J.L. Moll, "Two-Dimensional Modeling of Local Oxidation," presented at Device Research Conference, Colorado, June 1982.

[2.28] E.P. EerNisse, "Viscous Flow of Si02," Appl. Phys. Lett., 30, 1977, pp.

290-293.

[2.29] E.P. EerNisse, "Stress in Thermal Si02 during Growth," Appl. Phys.

Lett., 35,1979, pp. 8-10.

[2.30] D. Chin, S.Y. Oh, R.W. Dutton, and J.L. Moll, "Two-Dimensional Oxidation Modeling," IEEE Trans. on Electron Devices, ED-30, July

1983, pp. 744-749.

[2.31] D. Chin, S.Y. Oh, R.W. Dutton, and J.L. Moll, "Two-Dimensional

Local Oxidation," IEEE Trans. on Electron Devices, ED-30, Sept 1983, pp.993-999.

Chapter 3

Device Simulation

3.1 GEMINI: 2-D Poisson Solver

As the dimensions of MOS devices are scaled down, the device structures become more complicated. The insulator/semiconductor interfaces are often non-planar, and the impurity profiles of the devices are complicated and may not be expressed accurately in Gaussian form. The increased complexity of the device structure is necessary for optimization of the device performance, such as minimizing the drain-induced barrier-lowering effects, or enhancing the device reliability, e.g., reducing the electric field at the drain of the MOSFET. Therefore, in the development of VLSI MOS technology, it is essential to be able to simulate the electrical characteristics of devices which have complicated structures. The GEMINI program provides this capability.

The GEMINI program was developed at Stanford University by Greenfield and Dutton [3.1] in 1980. The program performs nonplanar VLSI device analysis by solving the 2-D Poisson equation. The program can accept data from the SUPREM and SUPRA programs, which provide high accuracy in the impurity profile definition, essential for submicron device simulations. The following sections will present in more detail the structure of the program as well as the input format, and then simple examples. In Part B of this book,

the use of the GEMINI program is presented in many case studies.

The Capability of GEMINI

Within the 2-D simulation system, the GEMINI program is linked to the SUPREM and SUPRA programs, as well as the PLPKG program for very flexible graphical output. SUPREM provides one dimensional vertical profiles such as the channel and source/drain profiles. This is very useful since the vertical profiles are usually non-Gaussian, an obvious example being source/drain profile. The lateral profile at the source/drain of the MOSFET is specified in the GEMINI input file in this case. If the 2-D process simulator SUPRA is used, then the whole device structure is specified, with the exception of the placement of the electrodes. The SUPRA-GEMINI combination is use- ful for the simulation of device structures with novel 2-D geometries such as the LDD structure [3.2]. The link between GEMINI and the PLPKG program allows the graphical output of quantities such as potential, impurity, carrier concentrations and electric field distributions, with very flexible format. 1-D, 2-D, as well as bird's-eye-view from different angles are possible. Fig. 3.1 shows schematically the linking of the GEMINI program with the other programs within the 2-D simulation system.

The GEMINI program can simulate device structures such as MOSFET, JFET, MESFET, SOS devices, and other non-planar insulator/semiconductor structures such as the trench isolation structure (this will be described in Chapter 10). Fig.3.2 shows three examples of structures whose electrical characteristics can be simulated by GEMINI. The structures shown are generated by the GEMINI program. The first one is a "channel length" simulation, where the device structure along the channel is defined. This is the structure that is most often simulated because it calculates the short channel effects where analytical or 1-D approximations are inadequate. The second example is a channel width simulation where narrow width effects such as threshold shifts are simulated. In this case, the capability of simulating non-planar insulator/semiconductor interface is essential. The third example shows an extreme case of a non-planar structure which is the trench isolation in CMOS [3.3] [3.4]. Here, the trench is 5 J.'m deep and 1 J.'m wide. All of these