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Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

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372

holding current, 246-247 initiating current, 233, 246-247 path, 234

Lightly-doped drain, 174,211-230, 297-298

processing, 214-215 simulation, 216, 297-298

Linear transconductance, 217 Linear-parabolic oxide growth model, 32

MINIMOS,14

MOSFET, 1-2

depletion mode, 326-333 enhancement mode, 317-326

Maxwell-Boltzman statistics, 90 Minimum overlap device, 229 Mobility

electron, 171,317 electron mobility model in CADDET,97

Gummel's bulk mobility model, 94 hole mobility model in PISCES-II,

104

modified Gummel's mobility model, 97

normal field mobility model for electron, 97

reduction, 320 Moving-boundary problem, 18

N-well

CMOS, 233-234, 277 dose, 146

Subject Index

Narrow width effect, 83-85, 235, 251 Navier-Stoke's equation, 60-61 Newton method, 105-106, 116 Newton-Richardson procedure, 106,

116

Numerical simulation system block diagram, 16-18 hierarchical simulation, 15 implementation scheme, 16-18 system support, 15-16

Obtuse triangle problem, 107 Oxidation

linear-parabolic growth model, 32 non-planar, 58-61

thin oxide, 35, 154-156 two-dimensional model, 59-61 volume expansion, 31

Oxide incompressibility, 61 thinning, 58 viscosity, 59

Oxide isolation SUPRA simulation, 53-54

Oxide encroachment LOCOS, 252-255 SWAMI,263

PISCES-II

1-D plot, 123-125

2-D contour plot, 122-123 I-V plot, 120-121

basic equation, 103 electrical characteristics

Subject Index

simulation, 113-119 grid generation, 107-111 initial guess, 106

input file, 108 numerical algorithm, 105 output, 119

PLPKG (see Plotpackage) Packing density, 235, 272

Parasitic bipolar transistors, 233-234 Parasitic components, 129

Pearson IV profile, 30,153-154 Performance, transistor, 174, 216-217 Plot package(PLPKG), 16-17,72-73,

88

Poisson equation in CADDET, 90 in GEMINI, 75 in PISCES-II, 103

Polysilicon gate n+,275-276 p+, 275

Potential barrier height, 201 Potential profile

n- pocket, 305 n-channel, 182,295-296 p-channel, 280-283 trench structure, 240-244

Power supply voltage, 181, 315 Process development, 6-8 Process simulation:history, 14-15 Program interface, 16

Projected range, 29 Punchthrough, 185-186, 198

bulk,201-206

373

current, 185 n-channel, 324, 197-208 p-channel, 206-207, 281 point, 203

surface, 201-206 voltage, 185, 198,324

Quasi-Fermi level, 183,240

Recombination

Auger, 104 Shockley-Reed-Hall, 104

Reliability, MOSFET, 212, 298 Residual current

n-channel, 169 p-channel, 285-286

SCAP2,13O

SIFCOD,14

SLOR (see Successive line overrelaxation)

SOAP

boundary conditions, 59-60 flow chart, 62

LOCOS simulation, 63-66 oxidation models, 59-61 SWAMI simulation, 263-264

SPICE, 19

SUPRA

device simulations, 178, 253, 265, 297

diffusion models, 49-53

ion implantation models, 47-48 LDD structure, 297

374

LOCOS simulation, 253-256 NMOS transistor simulation, 53-57 SWAMI simulation, 265-266

SUPREM

boron implantation, 153-154 diffusion models, 35-39

ion implantation models, 27-31 n-channel threshold simulation,

278

NMOS transistor simulation, 39-45 oxidation models, 31-35

oxygen enhanced diffusion of boron, 157-162

p-channel threshold simulation, 144-148,181,278

thin oxide growth, 154-156 SWAMI,261-268

Saddle point, 203 Saturation region, 171

Saturation transconductance, 217 Saturation velocity, 171, 273 Scaling, 1-6

constant field, 1-6 constant voltage, 3-4 depletion mode, 326-333

enhancement mode, 315-326 factor, 4-6

history, 1-2

Segregation coefficient, 39,157 Series resistance, 217, 317

Short channel effects, 3, 181, 190, 322-324

Simulation

basic device parameters, 180-186

Subject Index

methodologies, 143-148 tools,175-18O

Standard deviation, 29 Stone's method, 93 Stream function, 91-92 Stress, 263-264 Stress-relief oxide, 253 Strip line, 133

Substrate current, 212-213, 224, 227 Subthreshold characteristics,

168-169, 184 Subthreshold leakage, 169, 286

Subthreshold slope, 169-170, 281 n-channel, 169-170

p-channel, 281, 284-285 Successive line overrelaxation(SLOR), 79

Surface reaction rate coefficient, 31-32

TECAP2,19

Threshold current, 83, 183 Threshold voltage, 83, 160, 168, 170,

183,276

analytical calculation, 276 depletion mode MOSFET, 329 simulation, 180, 183 vs.channellength,288,190,297 vs. channel width, 258

Transconductance, 273 linear, 217 saturation, 217, 273

Transistor performance, 174,211

Subject Index

375

current drive, 174, 273 Transport coefficient, 31-32, 39 Trench,233

CMOS, 233-235

surface inversion, 235-248

Velocity Saturation, 4

Via hole capacitance, 355

Via hole resistance, 356

Viscosity, 59

Voltage standard, 4

About the Authors

Kit M. Cham was born in Hong Kong. He received the Ph.D. degree in applied physics from Yale University, New Haven, cr, in 1980. Since then, he has been with the Integrated Circuit Laboratory of Hewlett-Packard, Palo Alto, CA. He has worked on the characterization of MNOS devices for nonvolatile memories from 1980 to 1981. Since then he has been involved in the development of submicron CMOS technology. He is currently project leader for submicron CMOS device design. His work has resulted in 30 papers and two patents pending. He is coauthor of a book titled Computer-Aided Design and VLSI Device Development published by Kluwer Academic Publishers in 1986.

Soo-Young Oh received his Ph.D. in Electrical Engineering from Stanford University in 1980. He then joined Hewlett-Packard, and is now project manager of device, process, and system package modeling group in Structure Research Laboratory. He is currently working on a complete numerical simulation CAD system from process/device to circuit/system package. His work has resulted in 17 publications. He is a coauthor of a book titled

Computer-Aided Design and VLSI Device Development published by Kluwer Academic Publishers in 1986.

378 Computer-Aided Design

John L. Moll received his Ph.D. in Electrical Engineering from Ohio State University in 1952. He is currently senior scientist and manager of the Integrated Circuit Structure Research Laboratory of Hewlett-Packard. His extensive work in solid state devices has resulted in over 100 papers and ten patents. He is author of a book, Physics of Semiconductors, and coauthor of a book titled Computer-Aided Design and VLSI Device Development. He is a fel-

low of

IEEE, member of the American Physical Society, National

Academy

of Engineering, National Academy of Sciences, and Sigma Xi.

Keunmyung Lee was born in Korea in 1957. He received his M.S. and Ph.D. degrees from University of California, Berkeley, in 1982 and 1985, respectively, both in electrical engineering and computer sciences. Since 1985 he has been with Hewlett-Packard Laboratories, Palo Alto, CA. His current research interests are design and modeling of interconnect systems of integrated circuits and packages. He has published 8 papers, and has one patent pending.

Paul Vande Voorde recieved his Ph.D. degree in solid state physics from the University of Colorado in 1980. His dissertation topic involved fluctuation phenomenon in III-V semiconductors. He has worked at Hewlett-Packard Labon.tories since 1981. While at HP Laboratories, Paul has been involved in several silicon processing projects related to advanced CMOS. Currently he is working on process and device simulation to support CMOS and Bipolar process development. He has authored or coauthered 13 publications in journals and conference proceedings.

Daeje Chin was born in Korea in 1952. He received the Ph.D. in electrical engineering from Stanford University in 1983. He developed the twodimensional process simulation programs SUPRA and SOAP, for his dissertation at Stanford while working part-time at Hewlett-Packard I.C. Laboratory. After obtaining his doctorate, he joined IBM Watson Research Center in New

Authors

379

York. He has been working on submicron memory processing technology and high performance DRAM circuit design. In 1986, he joined Samsung Semiconductor, and is currently working on the development of 4MB DRAM. He has 15 publications and four patents pending. He is also coauthor of a book titled

Computer-Aided Design and VLSf Device Development published by Kluwer Academic Publishers in 1986.