Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

Fig. 15.16(a). Since the lines are paralle~ the two-dimensional calculation is an accurate simulation and is the same as the three-dimensional calculation. As the vertical spacing becomes larger, the capacitance decreases for both the two-dimensional and one-dimensional calculations. However, the relative error of one-dimensional calculation to the two-dimensional calculation becomes larger since the effect of the fringing field increases. For the 45° crossing lines in Fig. 15.16(b), we have to do the three-dimensional simulation to obtain a correct capacitance. As shown in Fig. 15.17(b), the twodimensional calculation underestimates the capacitance given by the threedimensional calculation, and the one-dimensional calculation underestimates it even more. Since the 9<Y' crossing has more three-dimensional characteristics than the 45° crossing, two-dimensional and one-dimensional calculations become almost useless. For the spacing of 1.5 ~m, the result in Fig. 15.17(c) shows that the two-dimensional calculation estimates the capacitance to be only half of the correct capacitance calculated by the three-dimensional calculation.

The above examples emphasize the importance of the three-dimensional simulation which most current circuit extractors do not consider. When they extract a circuit from its layout including interconnect capacitances, the extractors usually calculate them using a two-dimensional approximation, namely, areal and peripheral coefficients. But the smaller the size of interconnects and the greater the number of interconnect levels, the more inaccurate this approach is.

Fig. 15.18 shows another example of capacitance calculation of two-level interconnect lines. This time, three different dielectric materials are used to be more realistic. Due to the symmetry, half of the whole problem is simulated by cutting with a :xz-plane along the center of the second level metal (note the triad in the figure for the directions). Table 15.2 lists the amounts of charge on each conductor with a bias condition. Also, the potential plots in three ways - bird's-eye-view plot, contour plot, and one-dimensional plot - are shown in Fig. 15.19(a), (b), and (c). The bird's-eye-view and contour plots are the potential distribution on the plane, z = 2.4~, and the one-dimensional plot is

5.& 7.0 &.~

l.~

Fig. 15.18. Two-level on-chip metal lines simulated by FCAP3.

the high potential along the first-level center conductor (M12) and the suppressed potential due to the second-level conductor (M21) near the xzplane.

It is difficult to benchmark the above calculations against real measurements, since the values are too small to be measured directly. In fact, this is one of the main reasons that we have to resort to simulations to estimate the values. To verify the accuracy of three-dimensional calculations by FCAP3, we can build a scaled up structure and measure the capacitance of it. Fig. 15.20 shows a structure with metal bars and Table 15.3 lists the measured capacitance values for different configurations. The capacitance values simulated by FCAP3 and percentage difference between the measured and simulated values

capacitance per unit length of infinitely long cylinders. It underestimates the capacitance, especially when the diameter of the line is small, because it does not include the fringing field.

Via Resistance Calculation by FCAP3

2.6

2.6~

2.3

2.45

1.0

Fig. 15.22. A via connection of two-level on-chip metal lines. The shaded areas are contacts to the metal layers for the simulation

1.10.1292

1.350.1306

1.60.1320

1.850.1329

Table 15.4. Resistance of the via connection in Fig. 15.22 by FCAP3.

FCAP3 can calculate the resistance of a three-dimensional structure using the duality between capacitance and resistance as described in section 4.3. With this method, the resistance of a via connect in Fig. 15.22 is calculated varying the depth of the void at the center. The shape of the void depends on the multi-level metal process used. The result in Table 15.4 shows that the resistance does not change significantly. This is reasonable because the void is located where the current density would be low even if the void were filled [15.3].

References

[15.1] S. Seki and H. Hasegawa, "Analysis of Crosstalk in Very High-Speed LSI/VLSl's Using a Coupled Multiconductor MIS Microstrip Line Model," IEEE Trans. Electron Devices, ED-31, no. 12, pp.1948-1953, Dec. 1984.

[15.2] H. Hasegawa and S. Seki, "Analysis of Interconnection Delay on Very High-Speed LSI/VLSI Chips Using an MIS Microstrip Line Model," IEEE Trans. Electron Devices, ED-31, no. 12, pp.1954-1960, Dec. 1984.

[15.3] K. Lee, P. Vande Voorde, M. Varon, and Y. Nishi, "A Method to Reduce the Peak Current Density in a Via," Tech. Digest ofIEDM 1987.