Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

340 Computer-Aided Design

substrate. By varying the polysilicon line width, the fringing capacitance to the metal and substrate can be calculated. Fig. 15.4 shows the extraction of the parameters. The simulation shows that when the polysilicon line is covered by metal on the top, the fringing capacitance of the polysilicon line to the substrate is reduced by 60 %, since part of the fringing field has terminated at the metal plane.

Another interesting situation is for the case of metal over diffusion. Fig. 15.5 shows the two cases of metal line over diffusion plane (upper figure) and metal plane over diffusion line. The measured parasitic capacitance (in units of fF/ p.m2 for areal capacitance C4 and fF/ p.m for fringing capacitance CP) are shown for both cases. The thickness of the metal, low temperature oxide (LTO) and field oxide (F.OX) are 1.0, 0.5 and 0.5 p.m respectively. The fringing capacitance for the diffusion line to metal plane is much smaller than that of the metal line to diffusion plane. This is because at the side wall of the diffusion line, the effective dielectric thickness between the metal plane and the diffusion perimeter is much larger than the deposited oxide thickness. This is due to the shape of the field oxide in that region. This structure can be simulated by SCAP2 using the flexible input geometries described in section 4.2.

As mentioned in section 4.1, the interline capacitance of interconnections is becoming increasingly significant as the line spacings are reduced while the line thickness remains about the same. SCAP2 is used to simulate the case of metal lines with small spacings, and over a polysilicon plane. The simulated potential contour for the case of metal lines having different potentials is shown in Fig. 15.6. In this case, the line spacing is 0.8 p.m and the line thickness is 0.6 p.m. Fig. 15.7 shows the graph of the capacitance of the metal line versus line spacing for a case where the interlevel dielectric is a combination of nitride and oxide. The results show that the total line capacitance increases by 3E-3 fF/ p.m and l.3E-2 fF/ p.m when the line spacings are 2 p.m and 1 p.m respectively. The increase in capacitance is also dependent on the distance of the lines from the underlying conducting plane. If the distance is reduced, the interline capacitance will be reduced, since more of the field lines will be terminated on the conducting plane, thus reducing the coupling between the metal lines. Fig. 15.8 compares the two cases where the metal lines are above the substrate and above the polysilicon plane. The simulated results show that

Fig. 15.8. Simulated increases in metal line capacitance vs. metal line spacing for two metal lines at different potentials.

the increase in the total metal line capacitance with reducing line spacing (dC) is larger for the former case.

In the case where the potentials of the metal lines are the same, the total capacitance of two lines to the substrate decreases as the lines get closer to each other. (The extreme case would be when the line spacing· is zero, in which case the total fringing capacitance due to the side walls of the two lines would be reduced by a factor of two.) Fig. 15.9 shows the potential contour for this. case. By using the same technique as was discussed for the case of lines with different potentials, the reduction in the parasitic capacitance is calculated, as shown in Fig. 15.10.

Field Capacitance Calculation by SUPREM and GEMINI

When the capacitance involves the formation of a depletion layer with a width which is a significant fraction of the dielectric thickness, the SCAP2 program is inaccurate. This occurs in the case of the field capacitor, where the substrate underneath the field oxide forms a depletion layer, the depth of

which depends on the field implant profile. In this case, the depletion layer thickness is about O.lll-m, while field oxide is typically 0.5 to 0.6 Il-m. Poisson's equation has to be solved for a given bias condition, and then the capacitance must be calculated. The SUPREM program is used to simulate the impurity profile of the field implant under the field oxide. Then the profile is transferred to the GEMINI program, which creates the field capacitor, with the desired bias on the capacitor electrode and substrate. Fig. 15.11 shows the

potential contours from a GEMINI simulation of a polysilicon field capacitor. The symmetric boundary condition for the potential also allows one to considel the effect of periodic polysilicon lines biased at the same potential and separated by a specified spacing. This condition occurs in the polysilicon ser· pentine structure, and has the effect of reducing the fringing capacitance. Fig. 15.12 shows the extraction of the fringing and areal capacitances for all essentially isolated polysilicon line. The depletion layer formed at 5 V ha! significantly reduced the capacitance. Fig. 15.13 shows the effect of varyin~ spacing between polysilicon lines at the same potential, with fixed line width The reduction in the total capacitance is due to the reduction of the fringin~ component. The results shows that the reduction is not significant until the spacing is below 21l-m.

Diffusion Capacitance Calculation by SUPRA

Diffusion capacitance simulation involves the simulation of the electric field in heavily doped regions. The capacitance is a function of the impurity profile in the structure. Fig. 15.14 shows the simulation by SUPRA of the

Fig. 15.14. Two-dimensional simulation of the n+ profile by SUPRA. The dotted and solid contours are for boron and arsenic concentration (cm3) respectively.

impurity profile of an n+ diffusion region adjacent to the field oxide. The accuracy of the capacitance calculations depends very much on the accuracy of the doping profile. Careful analysis of the results shows that the accuracy of measurements is better than that of simulations. Thus measured data are used for circuit simulations. It is still useful to simulate the profile in this case because it provides a general picture of the impurity profile, and also indicates what will happen qualitatively to the capacitance if the processing steps are changed. The errors of the capacitance calculation reflect the difficulty of accurate process simulation for impurity profiles, particularly at the edges.

Interconnect Resistance Calculation by SCAPl

The resistance of a film of arbitrary two-dimensional geometry can be calculated using the SCAP2 program. Fig. 15.15 shows the simulation of the resistance of a two-dimensional shape. In order to use SCAP2 to calculate the

A B

Fig. 1S.1S. Resistance calculation for arbitrary two-dimensional shape.

resistance from contact (shaded areas) A to B, the materials of the contacts are defined to be metallic, and set at different potentials. The capacitance between the two metallic contacts are then calculated by SCAP2. The capacitance is related to the surface integral of the electric field at the metallic surface (the contacts A and B). This result can be converted into current flowing between A and B by replacing the dielectric constant between the contacts used in the capacitance calculation by the conductivity of the material under study. The total current flowing through the two contacts can thus be found for the bias condition specified, hence giving the resistance between the contacts. In this example, the calculated effective sheet resistance is O.38x(sheet resistivity). In other words, the 2-D shape between the two contacts is equivalent to 0.38 square in resistance.

Experiment and Simulation Comparisons

Measurements have been made on parasitic capacitance test structures with serpentine lines and are compared with simulated results. Examples of comparisons are shown in Table 15.1. The physical dimensions of the test structures were measured by SEM, and used in the simulations. Results show that the agreement is, in general, quite good. Note that in several cases of multi-layer structures such as polysilicon lines over field oxide and under a

Table 15.1. Measured and simulated data of parasitic capacitances.

metal plane, a combination of simulations and measurements is necessary to obtain the coefficients. Much improvement in the accuracy of circuit simulations has been obtained by using this methodology of parasitic capacitance extraction.

15.3 Three-Dimensional Parasitic Components Extraction

Muti-Ievel Interconnect Capacitance Calculations by FCAP3

A three-dimensional simulation is often necessary for the interline capacitance calculation in a multi-level interconnect system. To demonstrate the importance of a three-dimensional configurations for this problem, three situations of two-level metal lines over a ground plane are simulated: parallel lines, 45° crossing lines, and 900 crossing lines as shown in Fig. 15.16(a), (b), and (c). The interline capacitance values are calculated with respect to the vertical spacing between the first and second level metal by three different methods. The simplest method is a one-dimensional calculation. It does not consider any fringing field, that is, the capacitance values are obtained by multiplying the overlapping area with the areal coefficient for an infinite planar capacitor. The second method is a two-dimensional calculation. It includes the twodimensional fringing field using SCAP2, but it still does not include the threedimensional fringing at the corners of the crossing lines. The third and