Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

tax = 250A

Va = -2V

150 QNA= 1.17 x 101l/cm'

QND = 2.74 x 1011 / em,a Lm = 3.5 I'm

Wm = 314m

LINEAR SCALING

FROM 50 ~ DEVICE

IDS 100

--------------

1i'A1

Lm = 5 I'm

50

Fig. 14.8. Change of current characteristics of depletion mode devices due to change in channel length, with VGS

OV.

22.9, when LefJ is reduced from 49.25 J.'m to 2.75 J.'m, a factor of 17.9. The same trend is verified in the experimental measurement. For the case of LefJ = 2.75 J.'m, the curve of LefJ = 49.25 J.'m is multiplied by the scaling factor (= 49.25/2.75) and plotted in Fig. 14.8. It shows that the current in the linear region scales linearly, while the current in the saturation region has high output conductivity. The excessive slope in the saturation region adds extra transconductance at VDS = 5 V. This extra gain in the current by the LefJ scaling is opposite to the case of an enhancement mode device. The enhancement mode

short channel device shows mobility degradation in the linear region and considerable velocity saturation in the saturation region. All these effects combined cause the current gain factor of an enhancement mode device to be smaller than the Leff scaling factor. The device parameters of the unscaled and the scaled depletion devices are shown in Table 14.3.

14.4 Conclusions

CADDET is used intensively along with SUPREM to study the scaling schemes for MOSFET devices. It is shown that the MOSFET devices can be scaled to improve device performance. In case of an enhancement mode device, gate oxide thickness and channel length are chosen as prime scaling factors. The reduction in the gate oxide thickness increases the drain current, but the surface mobility degrades and this causes deviation from the linear scaling. The reduction in channel length promotes short channel effects, especially the saturation of the carrier velocity. After the punchthrough voltage is optimized, the final gain in the saturation current is 1.92.

In case of a depletion mode device, the depletion implantation dosage and the channel length become the major scaling factors. Since the current path is through the buried channel, the mobility is insensitive to the vertical field from the gate terminal. However, the excessive output conductance in the saturation region of the reduced channel length should be carefully controlled.

References

[14.1] R. H. Dennard et al, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," IEEE 1. Solid-State Circuits, SC-9, No.5, 1974, pp 256.

[14.2] E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York: John Wiley & Sons, Inc., 1982.

[14.3] R. C. Y. Fang, R. D. Rung and K. M. Cham, "An Improved Automated Test System for VLSI Parametric Testing," IEEE Trans. Instru. Meas., IM-31, no. 4, Sept 1982, pp. 198-205.

[14.4] L. A. Akers and J. J. Sanchez, "Threshold Voltage Models of Short, Narrow and Small Geometry MOSFET's: A Review", Solid-State Electronics, 25, No.7, pp 621-641, July 1982.

[14.5] D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, "SUPREM II - A Program for IC Process Modeling and Simulation," TR 5019.2, Stanford Electronics Laboratories, Stanford University, Calif., June 1978.

[14.6] A. S. Grove, Physics & Technology of Semiconductor Devices, New York: John Wiley & Sons, Inc., 1%7.

[12.7] L. D. Yau, " A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's", Solid-State Electronics, 17, pp. 1059-1063, Oct 1974.

Chapter 15

Examjlles of Parasitic Elements

Simufation

15.1 Introduction

In this chapter, the examples of parasitic component simulations are presented. The problems are solved by the appropriate simulation tools discussed in Chapter 4 and the other tools such as SUPREM, GEMINI, and SUPRA. Section 15.2 covers two-dimensional problems and section 15.3 deals with the problems which have to be solved by three-dimensional simulation. The experimental verification of the simulation results are also discussed.

15.2 Two-Dimensional Parasitic Components Extraction

Interconnect Capacitance Calculation by SCAP2

The areal and peripheral coefficients of parasitic capacitances between conductive layers can be investigated using the SCAP2 program. The structures range from the simple case of conducting lines over field oxide to more complicated cases of multi-layer coupling and interline coupling. Examples are:

(1)metal lines over field oxide, polysilicon layers, or diffusion

(2)polysilicon lines over field oxide

(3)polysilicon lines over field oxide covered by metal plane

(4)interline coupling of metal lines over polysilicon plane

Since SCAP2 does not accept semiconductor layers, the silicon layers are assumed to be conductors. This is a reasonable assumption for case (1), where the dielectric thickness is much larger than the depletion layer thickness in the silicon substrate and the bottom plane has high conductivity [15.1],[15.2]. However, when the polysilicon line goes over the field oxide (case (2) and (3», it forms a depletion layer on the surface of the substrate, the width of which is dependent on the impurity profile under the field oxide, and can be a significant fraction of the field oxide thickness. The GEMINI program is used for this case. This technique will be discussed in detail.

The simplest calculation would be that of a conducting line over a conducting plane (such as diffusion, or silicon substrate) separated by a layer of dielectric such as silicon dioxide, representing case (1). Fig. 15.1 shows such a simulation. The equipotential lines are shown (the electric field lines are perpendicular to the potential contours), which clearly show the importance of the fringing component, i.e., the component of capacitance arising from the two sides of the conducting line. For VLSI, the dielectric structure can be more complicated, and may contain a combination of different dielectric materials. This is due to issues such as planarization for better line width control. SCAP2 can also simulate these cases. The areal and fringing components of the capacitance are extracted by performing the simulation with different widths of conducting line. By plotting the total capacitance versus the line width, the slope of the resulting line and the extrapolation to y-axis will provide the areal and fringing components of the parasitic capacitance, respectively. Fig. 15.2 shows the result for the case where the interlevel dielectric is a combination of nitride and oxide.

As an example of the study of a more complicated structure, SCAP2 is used to simulate case (3) although the approximation that the substrate is metallic has to be made. Fig. 15.3 shows the structure generated by SCAP2. The program calculates the charge induced on the metal and substrate, hence

POLYSILICON

SILICON

SUBSTRATE

Fig. 15.3. Multi-layer capacitive coupling simulation.

500

400

E 300

.ii::s

(.)200

100 ,,",,"43

POLY LINE WIDTH (I'm)

Fig. 15.4. Extraction of multi-layer fringing capacitances.

the capacitive coupling to the two layers. The major interest here is in the fringing components to the two layers. The areal capacitance between the polysilicon and the upper and lower layers can be calculated independently, but the fringing component will be "shared" between the two layers. Hence it is wrong to use the fringing capacitance coefficients of the polysilicon line to separate metal or substrate planes. The fringing component to the two layers in this structure can be simulated by using essentially the same method as described in the previous discussion of a conducting line over a conducting

METAL LINE OVER DIFFUSION

PASS. METAL

LTO~II~II~~~~~~__IIL-

CP=O.054

CP=O.0056

METAL

CA=O.062

LTO

F.OX

P-SUB

Fig. 15.5. Comparison of fringing capacitance between metal line to n+ plane and n+ line to metal plane; units are in fF/p.m2 and fF/ I'm for area and peripheral components respectively.