Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

320 Computer-Aided Design

Scaling of Gate Oxide Thickness

As a first step in scaling, the gate oxide thickness (TItt) is reduced from 40 om to 25 om. This gives a scaling factor of 1.6 in TItt. The reduction in TItt increases the gate capacitance (CItt), which in turn increases the transconductance (gm) and the drain current. According to the classical model, the drain current is proportional to this scaling factor [14.6].

The threshold voltage (VT) depends on the implantation dosage to the first order, when the depletion boundary extends below the implantation region. CADDET simulations are done to study VT variation with implantation dosage for a fixed energy of 50 KeV. The boron implantation dose of 9.5Ell cm·2 was chosen to keep VT at 0.9 V. This process is designed to use a substrate bias of -2 V and thus all threshold voltages refer to this bias condition unless otherwise stated.

I -V characteristics of the device with the scaled TItt and the adjusted implantation are shown in Fig. 14.2. The important parameters of these characteristics are listed in Table 14.2. They show that the reduction in TItt causes a reduction in mobility of 8 %. This is due to the fact that the vertical electric field at the surface degrades the electron mobility. With a fixed gate bias, the thinner the insulator, the higher the electric field at the surface and the smaller the surface electron mobility. Fig. 14.2 shows that the saturation current at VGS = V DS = 5.0 V and V BS = -2 V is 14 mAo For the same bias condition, the unsealed device had a saturation current of 9.5 mAo Thus the current increases by a factor 1.47 in the scaled device. This number is close to the product of the scaling factor of TItt (= 1.6) and the reduction of mobility (= 0.92).

It should be noted that the increase in drain current at this stage of scaling does not always lead to an increase in circuit speed. The premise is true when the load of an inverter stage is dominated by parasitic capacitances, thus the increase in the gate capacitance does not affect the total load capacitance very much. So, for fixed load, the charging time is inversely proportional to the driving current. However, in case of a circuit whose load is dominated by gate capacitance, the scaling in TItt alone slows down the circuit speed, because the drain current increases by factor of only 1.47 while the load capacitance

increases by 1.6 in our case. Thus the load increases by a higher factor than the drain current. The present scaling in Tax should be followed by scaling in channellength, which requires readjustment of implantation dose and energy.

Scaling of Channel Length

With the gate oxide thickness sealed as discussed in the previous section, the mask channel length (L) is reduced from 2.0 jJ.m to 1.5 jJ.m. Assuming that the source/drain regions are formed by the same process technology before and after the scaling, this scaling reduces the effective channel length (LeJf) from 1.25 jJ.m to 0.75 jJ.m. This results in a scaling factor of 1.67. Since LeJf is less than one micron, the effects of reducing LeJf on the threshold voltage and

VT by implantation dosage (QNA) is simulated at 50 KeV. The implantation dosage of 1.17E12cm·2 is chosen so that VT for VBS = -2 V remains at 0.9 V. CADDET simulation is used to determine the device parameters which are listed in Table 14.2. The mobility is not affected very much by the channel length scaling. The simulated drain current at VDS = 5 V and VBS = -2 V is 17.4 mAo This is increased by a factor of 1.25 over that of the device with sealed oxide thickness but unsealed channel length. This is less than the scaling factor of channel length (1.67). The drain current for VGS = 5 V and VDS = 0.1 V increased by a factor of 1.59 which is close to the channel length scaling factor. Thus the saturation current increase of only 1.25 must be due to carrier velocity saturation in the channel. The resultant gain in saturation current for scaling both oxide thickness and channel length is 1.84, far less than the product of the two scaling factors (2.67) as predicted by the classical model.

With this fixed implantation dosage, the implantation energy is varied to study the subthreshold current and the punchthrough voltage. First, the subthreshold currents (ID at VD = 0.1 V, VBS = -2 V) are simulated in Fig. 14.3 with implantation energy ranging from 20 KeV to 50 KeV. The figure shows that the slope of the current is fixed at 74 mV/decade regardless of the energy.

14 r-----~--~~--~-----,----_,

Left = 0.75 ",m

Weft =48.5 ~

12Xj = 0.26 ~

~= 1.17 x 1012/cm2 tox = 250A

10

8

6

4

2

Fig. 14.4. Punchthrough voltage vs. implantation energy.

The implantation energy determines the position of the peak impurity concentration and the punchthrough current path. Fig. 14.4 shows the change of punchthrough voltage (VPT) as a function of implantation energy at fixed dosage. VPT is defined as a drain bias voltage at which the drain current is 1 nA per 1 p,m width at Vas = 0 V and VBS = -2 V. The figure shows that VPT is sensitive to energy and has a maximum value at 80 KeV. Above this value, VPT deteriorates due to the occurrence of surface punchthrough. Below this value, bulk punchthrough is the dominant current mechanism. It is known that the punchthrough voltage is very sensitive to the doping profile in the substrate. Our measurements show that the boron implantation follows the Pearson IV distribution rather than the normal distribution. If CADDET were upgraded to take different types of impurity distributions, the accuracy of the punchthrough simulation would improve.

The I -V characteristics of the scaled structure are shown in Fig. 14.5. The device parameters are extracted from these simulated curves and tabulated in Table 14.2 along with the previous results. The increase of implantation energy to 80 KeV decreases VT for VBS = -2 V to 0.8 V from its target value of 0.9 V at 50 KeV. The high implantation energy pushes the peak of the impurity profile deeper from the surface and the effective surface concentration decreases, consequently the threshold voltage decreases. The 0.1 V decrease in threshold voltage causes the linear and saturation currents to increase about 6%.

14.3 Scaling of a Depletion Mode MOSFET

CADDET Simulation

A depletion mode device fabricated on the same wafer as the enhancement mode device is chosen as a standard device. The mask dimensions of the gate are 3 Jl.m wide and 50 Jl.m long. The structural data of the device are the same as those of the enhancement mode device. The electrical characteristics of the device are shown in Fig. 14.6. The measured data are corrected for the voltage drop across the source and drain resistances. The difference in gm between VGS < 0 V and VGS > 0 V indicates the device has a buried channel.

To get the doping profile in the substrate, SUPREM is first run. The profile is converted to a sum of two normal distributions, one for the channel implantation and another for the depletion implantation. Then a CADDET input file is generated to simulate the device. The flat-band voltage (Vfl» is adjusted to give the correct magnitude of the drain current at VGS = 0 V. Once this adjustment is made, then the simulation of I -V characteristics shows good agreement with measurement in Fig. 14.6.

The scaling of the depletion mode device depends on the scaling result of the enhancement mode device, since the former is used as a load for the latter. In the following, the scaling scheme of a depletion mode device is discussed following the same steps as an enhancement mode device; the reduction in Tax, followed by the reduction in Leff. In each section, it is pointed out how the

scaling scheme for a depletion mode device is different from the scheme for an enhancement mode device.

Scaling of Gate Oxide Thickness

The current in the buried channel device in the linear region is closely proportional to the amount of the carrier charge in the channel, which is approximately given by

(14.1)

when Vas ~ VJb

where Qn is the electron density per unit area. QND and QNA are the dosages of depletion and channel implantations per unit area. The second term in the equation represents the accumulation charge when Vas is greater than VJb. The equation is valid when the depletion boundary lies deeper than the depth of the implantations and QND > > QNA. Eq. (14.1) indicates that the charge in the channel is determined by the net implantation dosage and is independent of Cox when Vas = VJb. In case of n+ poly gate device, the flat-band voltage (VJb) is determined by

when the voltage drop in the oxide due to the surface state charge (Qss) is negligible. N + in the equation is the doping concentration in the poly gate and Ns is the surface concentration in the substrate. Hence the magnitude of the VJb of an n+ poly gate depletion mode device is close to zero volt.

In real digital circuits, depletion mode devices are used almost exclusively with zero volt from gate to source. Hence the device operates practically at flat-band condition. Then, the parameters of importance are the current characteristics at zero gate to source voltage, which are governed by the dosages of implantations, and its sensitivity to substrate bias. Eq. (14.1) can be rearranged to

(14.3)