Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

estimated values for process control are used, then the statistical spread of device parameters can be estimated from the sensitivity matrix. The following shows the estimated 99.7% spread ("3-sigma" variations)of the device characteristics with/without n- pocket (units same as in Table 13.1(a),(b)):

u(Log(h)) = 1.7/2.7

U(VTLOW) = 0.1/0.1

u(6.CD ) = 0.2/0.017

a(6.VTLc) = 0.2 / 0.1

The indicated device parameter spreads show some differences between the n- pocket and conventional source/drain structure. The n- pocket device parameters has less variations due to short channel effects, but has more variations on the junction capacitance and long channel threshold voltage. The sensitivity matrix shows specifically the process variable that is the source of parameter variation. The comparison may be summarized as:

Advantages ofn -pocket:

1.Nearly eliminates the dependence of leakage and threshold voltage on gate length. This allows the long channel threshold voltage to be reduced from -0.8 V to -0.6 V.

2.Greatly reduces the dependence of subthreshold leakage and threshold on counter-doping dose and depth.

3 May be scalable to channel length less than 0.5 p.m.

Disadvantages:

1.Subthreshold leakage and threshold voltage become more sensitive to spacer width and p+ junction depth. These two parameters determine the size of the n- pockets.

2Process complexity is increased due to extra implant and perhaps one extra masking step. Subthreshold leakage and threshold voltage now depend on n- pocket implant parameters.

3Drain capacitance becomes sensitive to the n' pocket implant parameters and p+ junction depth.

13.4Conclusions

By using ~he SUPREM-PISCES programs, the sensitivity of the device electrical characteristics to process parameters variations can be systematically studied. In this particular case study, the sensitivity matrix shows that while the n' pocket design reduces the short channel problems, the structure introduces sensitivities to new processing variables. The desirability of using one or the other design depends on the controllability of various processes.

References

[13.1] K. M. Cham and S. Y. Chiang, "Device Design for the Submicrometer p-Channel FET with n + Polysilicon Gate," IEEE Trans. on Electron Devices, ED-31 , July 1984, pp. 964-968.

[13.2] S. Odanaka, M. Fukumoto, 'G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, "A New Half-Micrometer p-Channel MOSFET with Efficient Punchthrough Stops," IEEE Trans. Electron Devices, ED·33 , March 1986, pp. 317-321.

Chapter 14

MOSFET Scaling by CADDET

14.1 Introduction

The density and performance of integrated circuits have increased by many orders of magnitude through the process of device scaling. As pointed out in the overview chapter, the long channel relations are not strictly valid for horizontal dimensions that are comparable to the vertical dimensions. In this example, the operating voltage is kept constant. The horizontal dimension, Lejf, and the vertical dimension, Tax, will be separately scaled to approximately two-thirds of the established process values. The two scaling factors are not identical, but are in the typical scaling range. The result of this reduction is then established. Comparison with the long-channel scaling assumptions is possible, and the importance of secondary physical effects can be seen. Device width will not be scaled, the current drive capability will be expressed for a fixed width. Breakdown and punchthrough voltages must be sufficiently greater than the supply voltage so that reliability is not a problem. For this example, power density is not a limitation.

Two different modes of devices are considered, an enhancement mode device and a depletion mode device. Section 14.2 discusses how device simulation programs are used to study an enhancement mode device scaling and its

results are compared to the classical predictions [14.1]. Next, a scaling scheme of a depletion mode device is considered in Section 14.3 and is contrasted to the enhancement mode device scaling. Section 14.4 presents conclusions. The device simulation program CADDET is used throughout for numerical calculations.

14.2 Scaling of an Enhancement Mode MOSFET

CADDET Simulation

A typical n-channel enhancement mode device is chosen as a standard device to develop the discussion. The mask dimensions of the gate are 50 pm wide and 2 pm long. Structural data are collected by a series of measurements. The gate oxide thickness is 40 nm measured by c-v technique. [14.2] The measured effective channel length (Leff) and the source-drain series resistance are 1.25 pm and 750 {} per pm width respectively [14.3]. The electrical characteristics of the device are shown in Fig. 14.1. The measured data are corrected for the voltage drop across the source-drain series resistances.

The electrical characteristics of short channel length devices deviate from the classical model and do not conform to any known simple analytic expressions [14.4]. Numerical process and device simulation programs become very useful tools to study the characteristics of small geometry devices due to the built-in generality of the device structure and the accuracy in numerical computation.

CADDET is a 2-D device characteristics simulation program developed by IDTACID. The program solves Poisson's equation in the substrate with the current continuity equation for a single carrier only. It assumes that the surface of the substrate is planar and that the gate covers the entire substrate surface. In our application, the electron mobility in the program is replaced by a new expression given by Eq. (3.15). The substrate doping profile is simulated by running SUPREM [14.5], a 1-D process simulation program, which gives the doping profile in the substrate when the process sequences are specified (see Ch. 2). The source/drain profiles are also obtained from SUPREM.

Table 14.1. Conversion of SUPREM results to Gaussian formula.

Since CADDET takes only analytic expressions (such as normal distribution) for doping profiles, the results of SUPREM are converted to a normal distribution as shown in Table 14.1. Based on this data, the current-voltage (I-V) characteristics of the present (unsealed) enhancement mode device are simulated by CADDET and are compared with the measured data in Fig. 14.1. The device parameters that are important for digital circuits are listed in Table 14.2.