Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

concerns such as the hot electron effects and avalanche breakdown between the source and drain. This requires more complicated source/drain structures such as graded junction and LDD structures. The study of the source/drain structure becomes more important and Chapter 9 deals with this subject in detail using simulations. Computer-aided design has been shown to be essential in advanced device development where device structures are becoming more and more complicated due to many effects related to short channel devIces.

References

[12.1] F. Lee, N. Godinho, and C. P. Chiu, "Cool-Running 16K RAM Rivals N-Channel MOS Performance," Electronics, Oct 6,1981, pp. 120-123.

[12.1] Y. EI-Mansy, "MOS Device and Technology Constraints in VLSI,"

IEEE Trans. on Electron Devices, ED-29, Apr 1982, pp. 567-573.

[12.3] L. C. Thomas and J. J. Molinelli, "VLSI Logic," Tech Digest of ISSCC 1981, pp. 230-231.

[12.4] R. R. Troutman, "Recent Developments in CMOS Latchup," Tech. Digest ofIEDM 1984, pp. 296-299.

[12.5] D. B. Estreich, "The Physics and Modeling of Latch-up in CMOS Integrated Circuits," Stanford Electronics Labs Report #G-201-9, 1980.

[12.6] S. E. Laux and F. H. Gaensslen, "A Study of Avalanche Breakdown in Scaled N-Channel MOSFET's," Tech. Digest of IEDM 1984, pp. 84-86.

[12.7] C. Hu, "Hot Electron Effects in MOSFET's," Tech. Digest of IEDM 1983, pp. 176-181.

[12.8] K. M. Cham, D. W. Wenocur, J. Lin, C. K. Lau, H.-S. Fu, "Submicrometer Thin Gate Oxide P-Channel Transistors with P+ Polysilicon Gates for VLSI Applications," IEEE Electron Device Lett., EDL-7, Jan. 1986, pp.49-52.

[12.9] S. J. Hillenius, R. Liu, G. E. Georgiou, R. L. Field, D. S. Williams, A. Kornblit, D. M. Boulin, R. L. Johnston, W. T. Lynch, "A Symmetric Submicron CMOS Technology," Tech. Digest of IEDM 1986, pp. 252255.

[12.10] K. M. Cham and S. Y. Chiang, "Device Design for the Submicrometer p-Channel FET with n + Polysilicon Gate," IEEE Trans. on Electron Devices, ED-31, July 1984, pp. 964-968.

[12.11] D. V. Morgan, Ed., Channeling: Theory, Observation and Applications,

New York:Wiley, 1973.

[12.12] T. Kobayashi, S. Horiguchi and K. Kiuchi, "Deep-Submicron MOSFET Characteristics with 5nm Gate Oxide," Tech. Digest of IEDM 1984, pp.414-417.

[12.13] J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, "Generalized Guide for MOSFET Miniaturization," IEEE Electron Devices Lett." EDL-l, Jan 1980, pp. 2-4.

[12.14] S. Odanaka, M. Fukumoto, G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, "A New Half-Micrometer P-Channel MOSFET with Efficient Punchthrough Stops," IEEE Trans. on Electron Devices, ED-33, Mar. 1986, pp. 317-321.

[12.15] E. Takeda, Y. Nakagome, H. Kume, N. Susuki, and S. Asai, "Comparison of Characteristics of n-Channel and p-Channel MOSFET's for VLSI's," IEEE Trans. on Electron Devices, ED-30, June 1983, pp. 675-

680.

[12.16] H. Katto, K. Okuyama, S. Megure, R. Nagai and S. Ikeda, "Hot Carrier Degradation Modes and Optimization of LDD MOSFET's," Tech. Digest ofIEDM 1984, pp. 774-777.

[12.17] K. Balasubramanyam, M. J. Hargrove, H. I. Hanafi, M. S. Lin, D. Hoyniak, J. LaRue and D. R. Thomas, "Characterization of As-P Double Diffused Drain Structure," Tech. Digest ofIEDM 1984, pp. 782-785.

Chapter 13

A Systematic Study of Transistor Design

Trade-oft's

13.1 Introduction

The ability to manufacture circuits at, or near, fundamental density and speed limits is affected by the sensitivity of circuit parameters to variations in the manufacturing process, and by the ability to achieve tight control of the manufacturing process. Modifications of device or circuit design can alter the various dependencies, so that parts of the process that are intrinsically more controllable determine critical circuit properties. Critical dimensions determined by a series of steps (mask-making, exposure, develop, etch) are typically held to +j- 20%. Various ion implant doses and depths can be controlled to + j- 2% to 5%. For example, if there is an absolute minimum for channel length, then the circuit design must be set at L min +llL, where the yield of devices with L >L min is satisfactory and llL is a measure of the process variation with gate line width. L min must also allow for some overlap of the gate to source and drain. If the minimum channel length is set by a reliability factor, then the design target is determined by allowable early field failures rather than the allowable yield. This illustrates the difficulty in understanding the problems associated with scaling critical dimensions to less than 0.5 J.tm.

This chapter will not give a framework for solution of all the issues associated with submicron scaling, but present a method to systematically compare the sensitivity of two device designs on various process variables. The devices under study are the p-channel transistor with and without an n- pocket. The results are summarized in a matrix format so that the trade-offs of the two structures can be compared directly. This serves as a good example of how CAD can be used to systematically examine device structures for submicron applications.

13.2 P-Channel MOSFET with N- Pockets

The issues in the design of p-channel transistors with submicron channel length and n+ polysilicon gate have been described in Chapter 12. The major issue is the subthreshold leakage problem, which is caused by the counterdoping needed to adjust the threshold voltage [13.1]. One proposal for improving this situation involves the use of "n- pockets" [13.2] as shown schematically in Fig. 13.1. These pockets are formed by a relatively deep phosphorus implant before the sidewall spacer oxide is deposited. This extra doping effectively increases the n-well impurity concentration and also reduces the counterdoping depth near the source and drain regions. From the discussion in Chapter 12, the subthreshold leakage is expected to be reduced. Also, as the channel length is reduced, the n- pockets are brought closer together, making the effective n-well concentration higher with reducing channel length. This tends to counteract the threshold voltage fall-off problem.

The SUPREM-PISCES programs have been used to simulate the devices. Fig. 13.2(a) and 13.2(b) show a comparison of the potential distribution for a conventional device and one with the n- pockets. The reduction in the counter-doping junction depth and the depletion depth (the lowest potential contour in the figures) at the source n- pocket region indicates reduced short channel effects.

13.3 The Sensitivity Matrix

The sensitivity of the device parameters to process variations is of major importance to determine the manufacturability. We will consider the representation of the sensitivity in a general manner and apply this representation to the p-channel device.

A single device parameter, such as leakage current, is a function of various material and structural features such as junction depth, implant dose, etc. These features are, in turn, determined by processing conditions. The process will typically have a nominal value and allowable spread. The spread is typically determined by the ease of control of the equipment and environment as well as the ease of measurement of the feature or features that are most dependent on the process in question.

If all of the process controls are nominal (zero order) then we expect that the resulting features have their nominal values. The device or circuit parameters will also have their nominal values. It should be pointed out that presently available process models are not sufficiently accurate to give an exact relation between process conditions and device features. The approximate relation is generally adequate.

A general device simulator such as PISCES gives a functional connection between structural features and device parameters. We must be concerned with the statistical spread of device parameters from a process. If device features or process controls are chosen to be statistically independent, the analysis is relatively simple assuming that any given feature has a Gaussian probability distribution. That is to say:

where X is the particular feature Gunction depth, implant dose, etc.), X is the average or target value, u is the statistical spread, and P(X -X)M is the fraction of events that occur between X = X - X and X =X - X + M. The fraction of events occurring in the interval of X =X ± u, 20', 3u is 0.68, 0.95, 0.997 respectively.

If we consider electrical parameter variation around a nominal value, and if the variation is the result of Gaussian deviations of a process around its

nominal value, then for small variations the electrical parameter will be Gaussian. If the process deviations are statistically independent, the parametric spread is related in a simple way to the process spread. Thus

where V; is the ith parameter (voltage, current, etc.), V; is the nominal value, O'j is the ith statistical spread.

(13.3)

where O'j is the statistical spread of the ph process feature, and Ajj is the sensitivity of the parameter V; - V; to the jth process feature.

To compare design differences of p-channe1 transistors with and without n- pockets, ten process parameters were considered and five device characteristics were extracted. The target or nominal values of these parameters are listed in Table 13.1(a) and 13.1(b). The ten process features and 5 device parameters results in a 5 x 10 matrix of process sensitivity.

The exact representation of device parameter depends somewhat on the particular parameter. Log(h) is more convenient to use for leakage current than the current itself because the spread of current may be several orders of magnitude. The linear sensitivity is accurate for only a limited range of process variables. We chose to represent the process variables as fractional deviations from the target value. Fig. 13.3(a) and 13.3(b) show the calculated matrix Ajj and its connection between process and device for the n- pocket and conventional source/drain devices respectively. Note that within each matrix, there is no meaning in comparing the magnitude of the matrix elements, since they are dependent on the definitions of the process and device parameters. It is only meaningful to compare the same matrix element between the matrices in Fig. 13.3(a) and 13.3(b).

To extract further information from this matrix, it is necessary to analyze a given process environment so that each of the statistical variations can be estimated. For our purpose it is sufficient to know that the percentage spread on all of the processes except gate length is less than 10%. For short channel length, the control of gate length may easily be no better than 20%. If these