Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

source/drain junction is required, this will put a serious constraint on the temperature cycles of the subsequent backend process, such as interlevel dielectric reflow or planarization. It is always necessary to have estimates on the limiting values of these device parameters during process development.

Arsenic Implant Technique to Reduce }j

The conventional approach to the counter-doping process for adjusting the p-channel threshold voltage is the implantation of Bu at 25 KeV, which produces a junction depth of about 0.18 J.l.m. The simulated profile is shown in Fig. 12.4 in section 12.2. As has been shown, this counter-doping causes severe short channel effects such as subthreshold leakage. A new process to produce a shallow counter-doping junction depth has been developed with the help of simulations. This technique uses an arsenic implant immediately following a BF2 implant. BF2 is used because it reduces the channeling effect that is observed in the case of Bu. This produces a shallower junction compared with Bu. Furthermore, arsenic diffuses relatively slowly during process temperature cycles. It forms a steep profile at the counter-doping junction, and maintains a shallow junction depth. The simulation is shown in Fig. 12.15, and gives a junction depth of 0.09 J.l.m.

One major concern is whether this arsenic implant will introduce a much higher n-type impurity concentration near the surface, which will increase the capacitance between the p+ diffusion islands and the substrate. As can be seen in the simulation, the n-type impurity concentration is only slightly higher than the conventional technique. Also, the position of the depletion edge under the p+ diffusion will be beyond the peak of the arsenic profile which only extends to about 0.2 J.l.m. It is clear that this technique will not significantly increase the diffusion parasitic capacitance. One disadvantage of this technique is the process variation sensitivity. The boron channel implant is compensated by an arsenic implant, which requires good process control. Another disadvantage is that this technique requires an extra masking step to prevent the arsenic implant from going into the n-channel transistors. The n-well mask can be used and the hlignment is non-critical.

Submicron p-channel transistors with reduced short channel effects were fabricated using this technique. Fig. 12.16 shows the experimental data of the threshold voltage vs. effective channel length, for a drain to source bias of -2.5 V. The devices with larger values of lj showed more threshold roll-off as the channel length is reduced.

N- Pockets for Reducing Short Channel Effects

Another technique for reducing the short channel effects of p-channel transistors is the use of n- pocket [12.14]. This idea is similar to p- pocket for n-channel transistors. Fig. 12.17 shows the transistor structure and potential contours generated by PISCES. (See also Fig. 13.1 in Ch. 13). The n- pockets are produced by implanting phosphorus such that the peak of the impurity profile is above the bottom of the junction. Note that it is very desirable that the n- pocket not to be much deeper than that of the source/drain junction to avoid a significant increase of junction capacitance. The n- impurity concentration is typically 1E17 em-3. As the channel length of the transistor is reduced, the n- pockets of the source and drain are brought closer together, thus effectively raising the n-well impurity concentration. This increasing effective n-well impurity concentration tends to compensate the increasing short channel effects as the channel length is reduced. The idea is to maintain a stable threshold voltage down to Leff = 0.5 ISm and also to minimize the subthreshold leakage current. Fig. 12.18 shows the simulation of the subthreshold leakage current for p-channel transistor with and without n- pocket, for Leff = 0.5 ISm. The n- pocket design has a much lower subthreshold leakage current. The disadvantage of the n- pocket design is possibly an additional masking step, as well as sensitivity to spacer thickness and n- pocket implant variations. The trade-offs between p-channel transistor with and without the n- pocket is described in detail in Chapter 13, where a novel matrix approach is used to systematically study the sensitivity of the device characteristics to device design parameters.

Fig. 12.1S. Simulation of the subthreshold characteristics of p- channel MOSFET's with and without n- pockets, using the PISCES program.

12.3 N-Channel Transistor Simulations

Threshold and DIBL are less difficult to control in n-channel MOSFET's than in the p-channel counterpart. The n-channel transistor with n+ polysilicon gate requires a channel implant of the same type as the substrate, which reduces the short channel effects. Two-dimensional simulations are used to calculate the optimal channel implant profiles. There are other device issues that are more specific to n-channel transistors, which are also discussed in the following sections.

Concerns for Submicron N-Channel MOSFET's

There are two major device issues specific to n-channel transistors, in addition to the threshold voltage and DIBL control which are of general concern for submicron devices. They are the avalanche breakdown between the source and drain [12.6] and device performance degradation due to hot electrons [12.7]. The n-channel device is more susceptible to avalanche breakdown than the p-channel, because the impact ionization coefficient for electrons is much higher than that of the holes [12.15]. Also, for conventional source/drain structures, the n-channel transistor source and drain have more abrupt junctions, which means a higher electric field than the p+ junctions in the p- channel transistor. The higher ionization coefficient and the higher electric field cause a higher level of substrate current. This current produces a voltage drop across the substrate, which reduces the potential barrier between the source and substrate. Thus the channel current increases and produces more substrate current. This produces a positive feedback action which eventually causes the avalanche breakdown of the device.

Degradation due to hot carrier effects is more serious for the n-channel transistor compared with the p-channel transistor. This is because the electrons in the n-channel device have much higher ionization rate. Thus the understanding of the electric field distribution at the drain region as a function of the drain structure is very important for the n-channel MOSFET. New device structures such as the Lightly-Doped Drain (LDD) structure have been developed to reduce the electric field. The electric field can be simulated by the CADDET or PISCES programs. This is presented in detail in Chapter 9.

Threshold and DIBL Control

The threshold of the n-channel transistor as a function of the channel profile can be simulated by SUPREM for the long channel, and by the combination of SUPREM and GEMINI or PISCES for the short channel transistors. The channel profile will depend on the application of the devices, as well as the structural parameters such as gate oxide thickness. For example, the amount of doping will be less if negative substrate bias is used in the circuit. In the

discussion below, the substrate bias is assumed to be zero, as is the case in most CMOS circuits.

From the discussion in the previous section, it can be seen that for p- channel transistors with channel length of 0.5 pm, a thin gate oxide of 15 om must be used to reduce the residual leakage current. Hence the channel implant for the n-channel transistor will be based on this gate oxide thickness. Fig. 12.19 shows the channel profile which will produce a threshold voltage of 0.5 V for long channel transistors. But the threshold voltage will be reduced when the channel length is reduced to 0.5 pm, and the drain bias increased. This is studied by coupling the channel profile with the GEMINI program, and specifying the desired drain bias. Fig. 12.20 shows the results of such a simulation. The DIBL effect is evident from the shape of the potential profile which extends from the drain towards the source. The high impurity surface concentration has prevented the punchthrough problem near the surface. This reduces the leakage current under a drain bias of about 3 V, where the potential barrier minimum point is found to be at the surface. At higher drain bias, the punchthrough current path will be through the more lightly doped bulk. The reason for this has been explained in Chapter 8.

The threshold voltage as a function of the effective channel length is simulated for the case of 15 om gate oxide and a drain bias of 3 V, using the GEMINI program. The result is shown in Fig. 12.21. The threshold roll-off is quite significant at Leff of 0.5 pm, but is still tolerable for most applications. The roll-off can be reduced by using a higher channel implant dose, at the expense of lower current drive, higher junction capacitance and body effect (see Table 7.1 in Chapter 7).

Source/Drain Structures

The source/drain structure of submicron devices is determined by several considerations. The first is the high electric field near the drain. This causes hot carrier degradation problems as well as avalanche breakdown, as mentioned previously. Two types of drain structures are used for reducing the electric field. They are the LDD [12.16] and the double diffused junction [12.17] structures. The double diffused drain structure uses a

combination of arsenic and phosphorus implant to form a more graded junction, thus reducing the electric field at the junction. The LDD structure is formed by using a low dose tip implant before the formation of the side-wall spacer, followed by the formation of the spacer and the n+ diffusion region. Fig. 12.22 shows the simulation of such a structure using the SUPRA program. The tip implant reduces the electric field because of the light doping. The detailed analysis of the LDD structure and its effect on the drain electric field is presented in Chapter 9.

The second consideration in the source/drain structure is process control. For submicron gate length, side-wall spacers are commonly used. This means that either a tip implant is used, or the source/drain region has to be diffused far enough into the channel region to ensure overlap between the gate and the n+ regions. In this respect, the tip implant is more desirable since the overlap is guaranteed, independent of side-wall spacer thickness variations. Also, the tip junction depth is only about 0.1 pm, which reduces the punchthrough problem at short channel lengths, for the same amount of gate to source/drain overlap.

The third consideration is the process complexity. In NMOS technology, the tip implant does not require additional masking. But for CMOS, the tip implant requires an additional mask since the p-channel device has to be masked during the tip implant. The source/drain structure of the submicron n-channel transistor has to be determined by the application of the device. In any case, the conventional arsenic structure will not be adequate due to reliability problems. Either double diffused junction or LDD must be used.

12.4 Summary

The design of the n and p-channel transistors for the submicron n+ polysilicon gate CMOS process has been presented. The major concern for the p-channel transistor is subthreshold leakage due to the counter-doping. Using simulations, the device can be designed to minimize the short channel effects. For the n-channel transistor, the leakage problem due to short channel effects is not as severe. But the n-channel transistor has more reliability