Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

boron channel implants. If inversion is a major problem, then the n-channel transistor has to be put at a distance of about 1 J.tm away from the trench, where experimental results showed that leakage is not a problem.

References

[10.1] S.-Y. Chiang, K. M. Cham, D. W. Wenocur, A. Hui, and R. D. Rung, "Trench Isolation Technology for MOS Applications," Proc. of the First International Symposium on VLSI Science and Technology, 1982, pp. 339-346.

[10.2] R. D. Rung, H. Momose, and Y. Nagakubo, "Deep Trench Isolated CMOS Devices," Tech. Digest ofIEDM 1982, pp. 237-240.

[10.3] K. M. Cham and S.-Y. Chiang, "A Study of the Trench Surface Inversion Problem for the Trench CMOS Technology," IEEE Electron Device Lett., EDL-4, Sept 1983, pp. 303-305.

[10.4] T. Yamaguchi, S. Morimoto, G. H. Kawamoto, H. K. Park, and G. C. Eiden, "High Speed Latchup-Free, 0.5 J.tm-Channel CMOS Using SelfAligned TiSi2 and Deep Trench Isolation," Tech. Digest of IEDM 1983, pp. 522-525.

[10.5] D. B. Estreich, "The Physics and Modeling of Latch-Up in CMOS Integrated Circuits," Stanford Electronics Labs Report #G-201-9, 1980.

[10.6] R. R. Troutman, "Recent Developments in CMOS Latchup," Tech. Digest of IEDM 1984, pp. 296-299.

[10.7] K. M. Cham, S.-Y. Chiang, D. W. Wenocur, and R. D. Rung, "Characterization and Modeling of the Trench Surface Inversion Problem for the Trench Isolated CMOS Technology," Tech. Digest of IEDM 1983, pp.23-26

[10.8] C. W. Teng, C. Slawinski and W. R. Hunter, "Defect Generation in Trench Isolation," Tech. Digest ofIEDM 1984, pp. 586-589.

[10.9] S. M. Sze, Physics of Semiconductor Devices, second ed., New York:Wiley-Interscience, 1981.

[10.10] A. S. Grove, Physics and Technology of Semiconductor Devices, New York:Wiley, 1967.

Chapter 11

Development of Isolation Structures for Applications in VLSI

11.1 Introduction to Isolation Structures

Device isolation has become one of the major issues in VLSI. As more and more devices are packed together on a single chip, the spacing between devices is reduced significantly. Island width/space design ru1es are becoming very aggressive, in the range of 1 p.m/1 p.m [11.1]. This means that the width of the isolation structures has to be scalable without causing field leakage problems. Also, as the transistor widths are scaled down, to the range of 2 p.m or less, narrow width effects become a major issue [11.2]-[11.5]. These effects are dependent on the isolation structures since the channel width of the device is defined by the field isolation. Many novel isolation structures have been investigated for applications in VLSI [11.6]-[11.14].

In general, there are several considerations in the design of isolation structures. First, the isolation dielectric thickness should be as thick as possible. This will provide a higher field threshold voltage, as well as a lower parasitic capacitance for conducting lines over the field oxide. Second, the field isolation should not encroach significantly into the island area (active area). In VLSI, over a million transistors may be packed on a chip, which

(micron)

Fig. 11.1. Field oxide and boron encroachment in LOCOS.

means that the transistor size is a major consideration. Drawn channel widths (i.e., mask dimensions) are being scaled to the 1 p.m range in advanced integrated circuit development [10.15]. Any encroachment of the field isolation into the active area will cause a significant reduction in the current drive of the device. This problem is shown schematically in Fig. 11.1 for the case of LOCOS isolation. [11.16]. The effective channel width of the device is significantly smaller than the drawn width. The slope of the field oxide at the boundary of the active area is also a consideration. If the slope is shallow as is the case for LOCOS, then this causes an increase in the threshold voltage of the transistor as the device width is scaled down. The threshold increase occurs because the gate electric field spreads into the field area, causing an increase of the effective channel doping of the device. Also, if a lightly doped substrate is used, a field implant of an impurity of the same type as the substrate is necessary to produce the desired field threshold voltage. In this case, the impurity may diffuse into the active area during processing, thus causing an increase in the threshold voltage or a loss of effective channel width of the active transistor. These problems of oxide and boron encroachments will be discussed in more detail later for the case of LOCOS isolation. Third, the isolation structure is preferred to be planar with respect to the silicon surface so that subsequent steps in photolithography and etching will not be affected by topological problems. A planar surface, for example, will minimize necking of

narrow polysilicon lines running across an island/field edge. The last consideration, but not the least, is process complexity. It is highly desirable that any novel isolation structures be compatible with existing MOS processes, and not require additional masking steps.

From the above discussions, it can be seen that in most cases, compromise must be made to optimize the design of the isolation structure. Simple isolation techniques such as LOCOS result in oxide encroachment. Higher implant dose to maintain the field threshold results in higher diffusion capacitance. The use of thicker field oxide to reduce interconnect capacitance may result in more oxide encroachment as well as more complicated processing problems due to topology. The following sections describe the design of isolation structures, using simulation programs as tools to optimize the design. The discussion begins with the simplest isolation technique, LOCOS. Then, modifications of this technique to minimize oxide and boron encroachment are discussed. Finally, a new isolation technique, SWAMI, is presented, which will be shown to solve most of the concerns mentioned above.

11.2 Local Oxidation of Silicon (WCOS)

LOCOS [11.16) has been used in most integrated circuits up till this date. The process is very simple and well known. Only a brief description will be presented. The process is shown in Fig. 11.2, using the output of the SUPRA simulation. A layer of thin oxide (stress relief oxide) is grown above the silicon substrate. This is followed by a layer of nitride. Then the nitride is patterned using photolithography technique, followed by plasma etching. This defines the regions of field and active area. Then a field implant is performed to increase the threshold voltage at the field. The photoresist is then removed followed by oxidation of the exposed silicon area. The simulation shows that the encroachment of the oxide is very significant. For this case, the encroachment is about 0.3 J1.m on each side for a field oxide thickness of 0.55 J1.m. This oxide encroachment is mainly due to the presence of the stress relief oxide underneath the nitride, which is necessary to avoid defects in the active area of the silicon. The oxygen diffuses through this oxide layer during field oxidation, and hence oxide

is grown under the nitride layer near the field edge.

Another concern with LOCOS is the encroachment of the boron impurities into the active area. If the impurity concentration underneath the active area is significantly changed, then this will cause a reduction of effective channel width, and may also cause an increase in the threshold voltage of the active transistor. In order to see how serious is the problem, the SUPRA program is used to simulate the 2-D structure, and the output data is coupled to the GEMINI program to calculate the current-voltage characteristics of the transistor in the linear region. Fig. 11.3 shows the simulated cross-section of the width of the transistor. The LOCOS isolation structure together with the field and channel implant impurity profile are shown. The simulated depletion region indicates that part of the gate electric field has terminated into the field region, hence there will be an effect on the electrical characteristics of the device.

Fig. 11.4 shows the simulated current-voltage characteristics of transistors with varying drawn widths (WD). IDs/WD is plotted versus VGS for drawn channel widths from 1 to 4 p.m as well as for a very wide device of 104 p.m. If the isolation is ideal, such that the electrical channel width and the drawn channel width are the same, then all of the curves will be identical to that of the wide device, since IDs is proportional to the effective channel width. The simulated results show that for LOCOS isolation, this is not the case. The value IDs/WD decreases rapidly as WD is reduced to 1 p.m. This clearly shows that LOCOS is not acceptable for VLSI.

The effective width of the transistors can be calculated from these simulated results. Since the transconductance, given by the slope of the IDs vs. VGS curve, is proportional to the effective channel width of the device, a plot of the transconductance versus the drawn channel width will provide us the value of the channel width loss due to the isolation process. Fig. 11.5 shows the extraction of the channel width. The actual width is found to be 0.7 p.m less than the mask width.

The channel width loss can be due to both the oxide encroachment and the boron field implant which diffuses into the active area, causing an increase of the threshold voltage at the active area edge. The latter effect can be studied by comparing the simulated current-voltage characteristics of a narrow