Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

N-WELL(3V)

(MICRONS)

Fig.tO.7. 2-D potential profile of the trench isolated CMOS structure. The n-well bias is 3 V.

region. The bias conditions are 0, 3, -1 volts at the n+, n-well and substrate respectively. The p-type channel implant profile which overlaps the n+ region has been neglected in this case for simplicity. The shape of the potential contours indicates that the n-well and Qss both have the effect of raising the potential at the trench surface opposite to the n-well. It is interesting to look at the potential along the trench surface from the n+ to the nowell, as follows:

The path along the trench surface from the n+ to the n-well can be viewed as the channel of a MOSFET with the n+ as the source, the n-well as the gate and the drain, although part of the channel is not under the gate. From the results of the two-dimensional simulations, the potential along this path can be plotted. Fig. 10.8 shows the potential profile for different cases. The first case is for no surface charge and zero n-well bias, as a reference. The second case shows the effect of increasing the n-well bias to 3 V. The potential in the region opposite to the n-well is raised, as expected. The approximate quasi-Fermi level is also shown. The quasi-Fermi level is a function of the biases at the n+ and n-well. The condition for inversion is similar to the gated diode structure [10.10]. If the potential is above the quasi-Fermi level, then inversion occurs. In this case, it is clear that no inversion has occurred, as expected. The third case is for a positive charge density of 5E10 cm-2 at the trench surface, and with an n-well bias of 3 V. The potential near the n+

QSS=POSITIVE FlXED CHARGE DENSI1Y

NA=BULK DOPING CONCENTRATION

VW=N-WELL BIAS; VB=SUBSTRATE BIAS

Table 10.1. Summary of trench simulations.

ranges from 0 to 3Ell cm·2, and the bulk doping concentration ranges from 6E14 to 1E16 cm-3 • N-well biases of 0 V and 3 V and substrate bias of 0 to -3 V are considered. Table 10.1 summarizes the results of the simulations. The cases to be considered are put into four groups. The first group studies the effect of increasing Qss. The second group studies the effect of increasing substrate doping. The third group studies the effect of substrate bias and the last studies the effect of n-well bias. Also indicated in the last column is a qualitative description of the simulated results. The n+ region is biased at 0 V. In all cases, the p-type channel implant overlapping the n+ region is taken into account.

From the first three rows of Table 10.1, the results show that with a substrate bias of -1 V, and p-substrate doping of 6E14 cm-3 , trench surface inversion occurs if Qss is greater than SElO cm-2 • The second group, from the third

doping has to be raised to 2E15 cm-3 and 1E16 cm-3 respectively in order to avoid trench surface inversion. The substrate bias effect is shown from the '1-h to the 9th row. The substrate bias shows little effect in preventing inversion if Qss is 1Ell cm-2 and p-substrate doping is 6E14 cm-3, although it is found that at lower Qss values, negative substrate bias reduces the probability of inversion. The last row shows that for a Qss value of 1Ell cm-2, the inversion can be avoided if n-well is biased at zero volt. This merely serves to reveal the effect of the n-well bias. The n-well has to be biased to a positive voltage for the circuit to function, and the results show that minimizing the n-well bias will reduce the probability of inversion.

10.5 Experimental Results

The trench surface inversion problem has been studied experimentally and compared with the simulated results. The problem of trench surface inversion is manifested in the subthreshold characteristics of the n-channel transistor, as shown in Fig. 10.13. The transistor which is essentially adjacent to the trench shows severe leakage problem, while the transistor at a distance of 1.5 p.m away from the trench has no leakage problem, and is electrically indistinguishable from LOCOS isolated transistors. The p-channel transistor has no leakage problem, and is similar to non-trench devices. This indicates that the problem is positive charge on the trench surface or in the refilled material which causes inversion along the trench surface in the p-substrate region.

The effective charge density at the trench surface was determined by the trench surface inversion test structures [10.7]. The value was found to be 1.8Ell cm-2• Comparison with Table 10.1 of the simulation results shows that a p-substrate doping concentration of at least 5E15 to 1E16 cm-3 is necessary to avoid inversion, which means that p-well CMOS is a better choice for the application of trench isolation.

Experimental results have also shown that when the trench surface is inverted, the latchup resistance of the trench structure is not as high as expected. Table 10.2 shows the results for the measurements of the latchup

initiating and holding current levels for the trench and non-trench structures. The difference is quite small, although the trench structure has an n+ to p+ spacing of 4 ~m, which is much smaller than the conventional test structure, of 8 ~m. The latchup resistance of the trench structure is much less than expected in this case, and is due to the existence of the inverted channel along the trench, all the way to the n-well. If this conducting path to the n-well is disconnected, for example, by a p-type implant into the trench [10.4], the latchup resistance will be recovered and would be much better than the conventional LOCOS structures.

10.6 Summary

By using two-dimensional simulations, the problem of trench surface inversion has been studied in detail to investigate the possibility of placing the transistors adjacent to the trench. Different conditions of charge density, biases, and doping concentrations have been considered. The regions of inversion have been identified. The results show that if Qss is larger than 5E10 cm-2, then inversion will likely occur, unless the p-substrate doping concentration is increased. If Qss is larger than 1Ell cm-2, then powell CMOS is more suitable for the application of trench isolation, due to the much higher doping concentration in the powell. By minimizing the n-well bias, the probability of inversion is also reduced. Experimental results indicated Qss values of about 2Ell cm-2. Latchup resistance of the trench isolated structures with the transistors adjacent to the trench side-wall showed only slight improvement over the LOCOS isolated structures, under the condition of surface inversion. This indicates that the inversion path between the n+ region and the n-well has to be disconnected in order to recover the trench resistance to latchup. This can be done either by implanting into the trench, or by using p/p+ epi where the trench bottom is within the p+ region. Trench isolation is more suitable for powell CMOS, where the inversion problem can be put under control if Qss is not too large. If body effect and diffusion capacitance are not of major concern, then trench isolation can also be used for n-well CMOS or NMOS processes by using a lower resistivity substrate, or using high dose and deep