Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

the physics of the effects can be readily investigated by looking at potential, electric field and electron distributions in the simulated device.

Drain Electric Field and Substrate Current Study

The drain electric field characteristic of LDD device is simulated by putting the n- region at the drain side. The drain electric field as a function of n- region doping, n- region length and the amount of gate overlap of the n- region is studied. Several interesting results are obtained through the simulation and are confirmed experimentally by looking at the substrate current characteristics. Important physical insight into the operation and design of LDD device, conventional device and minimum overlap devices are obtained.

A) Drain electric field as a function of n- region dose

In the simulation of drain electric field characteristic as a function of n- region doping, it is found that, contrary to common belief, lower n- region doping doesn't necessarily lead to lower drain field. Fig. 9.10 plots the simulated drain peak field versus n- region implant dose for n- region length of 0.2 micron and a bias condition of S V at the drain and 3 V at the gate. A minimum peak field is found at a dose of SE12. Physically, for the lowly doped case (2E12), the entire n- region is depleted and a high field occurs at the high-low junction. For the higher doping (lE13), it is harder to deplete the n- region and the peak field occurs at the edge of the n- region. Experimental results confirm this finding. Fig. 9.11 plots the drain voltage needed to generate 1 pA per micron of channel width of substrate current versus the n- region implant dose. It can be seen that the highest drain voltage required is at a dose of SEl2. This optimum dose for breakdown and lowest substrate current will vary to a certain extent with the n- region length. Although SEl2 gives the best breakdown and substrate current characteristics, the series resistance is high as shown in Figures 9.4 to 9.9. Another consideration is that lower substrate current does not necessarily lead to lower hot electron trapping. All these factors need to be considered in the optimum design of the dev-

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B) Drain electric field versus gate voltage characteristics

According to Eq. (9.1a), in the conventional device the maximum drain electric field is directly proportional to VD-VDSAT• Since V DSAT increases with VG (Eq. (9.1b», the drain electric field decreases with increasing gate voltage. From Eq. (9.2), reduction in drain electric field means the substrate current will also decrease with increasing gate voltage. Fig. 9.12 shows the measured substrate current versus gate voltage characteristic of a conventional device. It can be seen that after an initial peak, the substrate current does decrease with increasing gate voltage. The initial increase of substrate current with gate voltage is due to increase in channel current.

The drain electric field versus gate voltage characteristic is simulated for LDD structures with different n· region doping and amount of overlap between the gate and the n· region. The electric field at the surface along the channel is plotted for each bias point and the position where the peak electric field occurs is noted. Fig. 9.13 shows a plot of the simulated electric field along the channel for the bias point of VG = 3 V and VD =6 V. The electron concentration as a function of Y ( the distance from silicon/silicon dioxide interface into silicon) is then plotted at the position of the channel where peak electric field occurs. The position where peak electron concentration occurs is noted. Depending on the device structure, the peak electron concentration in some cases is not at the surface. The electric field along the channel is then plotted again at the Y position where peak electron concentration occurs. Then the maximum drain electric field is found from this plot. Fig. 9.14 is a plot of maximum drain electric field as a function of gate bias for different amount of gate overlap at a n· dose of 1E13. It can be seen that for low VG , the drain electric field is greatly reduced when the gate overlaps the n° region more. Another observation is that the drain electric field is actually not a very sensitive function of gate voltage for half micron LDD device for X larger or equal to 0.2 p.m. Fig. 9.15 is a similar plot for a n° region dose of 5E12. The characteristic is very different from that of Fig. 9.14. It can be seen that the electric field initially decreases with increasing gate voltage, reaches a minimum and then goes up again. The smaller the gap between the gate and the n+ junction, the higher the electric field goes up. This effect was confirmed in experimental devices. Fig. 9.16

Fig. 9.14. Maximum drain electric field vs. gate bias for n- dose of 1E13.

shows substrate and gate current versus gate voltage characteristics for LDD devices with a n- region doping of 5E12 and different n- region length. A double hump is observed in the substrate current characteristics which correspond to a decreasing and then increasing electric field.

The physics of this phenomenon can be understood by looking at the potential, electric field and carrier density along the channel. Fig. 9.17 plots the channel potential and electric field for VG = 2 and 8 V. It can be seen that at VG = 2 V, most of the drain potential is dropped in the n- region overlapped by the gate (X) and the peak electric field occurs at the edge of the n- region. For VG = 8 V, most of the drain potential is dropped in the region between the gate edge and the edge of the n+ junction (Y) and the peak electric field occurs

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Fig. 9.15. Maximum drain electric field vs. gate bias for n- dose of SE12.

at the Hi-Lo junction. In the latter case (VG = 8 V), the shorter the distance Y, the higher is the electric field because the potential is dropped in a shorter distance. The way the potential and electric field behave under different gate bias conditions is found to be due to the fact that at high gate bias the channel carrier density can be comparable to the doping concentration of the n- region. At VG =2 V, the channel carrier density is less than the n- region doping concentration. The n- region under the gate is mostly depleted and most of the drain potential is dropped there. The peak electric field occurs at the edge of the n- region. However, at VG = 8 V, the channel carrier density is comparable to the n- region doping concentration ( for the SE12 case), therefore the n- region under the gate can no longer be considered depleted. The space charge region is pushed towards the heavily doped n+ junction and the potential IS then dropped in the region Y. The position of the