Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

can be seen to be at the surface for bias point A and at the bulk for bias point B. This identifies the surface and bulk punchthrough for the two cases. The punchthrough paths can best be illustrated by the current vectors generated by the PISCES simulations. Fig. 8.10 shows the current vectors for an n-channel transistor with VGS = 0 V and V DS = 3 V. The Leff is 0.5 I'm. The device has no deep boron implant for bulk punchthrough resistance. The current vectors indicate that current is flowing along the surface and through the bulk. The bulk punchthrough path has a maximum depth of about 0.6 I'm from the silicon surface. A boron implant of 70 KeV and a dose of about 1E12 cm-2 will eliminate the bulk path.

Another interesting punchthrough phenomenon is shown in Fig. 8.11 for a p-channel transistor with n+ polysilicon gate. The transistor has a counterdoping in the channel for threshold voltage adjustment (see Ch.12). In this case, the punchthrough path is through the entire counter-doping layer, with a layer thickness of about 0.2 I'm. This result indicates that the counter-doping causes serious punchthrough problem at short channel length. This is a major concern for submicron CMOS using n+ polysilicon gate.

Overall the simulations agree with the experiment very well qualitatively. To agree quantitatively well with experimental data, one needs very precise process simulations of the channel and source/drain profile, and also very accurate experimental data such as the effective channel length. Therefore, very good quantitative agreements for short channel devices at high drain biases are difficult to obtain. But still one can gain a lot of insight and have good estimates on the punchthrough behavior of submicron channel length MOSFET's.

References

[8.1] R. R. Troutman, "VLSI Limitations from Drain-Induced Barrier Lowering," IEEE Trans. Electron Devices, ED-27, April 1979, pp.461-

468.

[8.2] R. R. Troutman, "Subthreshold Design Considerations for Insulated Field Effect Transistors," IEEE I. Solid State Circuits, SC-9, April 1974, pp.55-6O.

[8.3] B. Eitan and D. Frohman-Bentchkowsky, "Surface Conduction in Short Channel MOS Devices as a Limitation to VLSI Scaling," IEEE Trans. Electron Devices, ED-26, April 1979, pp. 254-266

[8.4] H. Masuda, M. Nakai, and M. Kubo, "Characteristics and Limitation of Scaled-Down MOSFET's Due to Two-Dimensional Field Effect," IEEE Trans. Electron Devices, ED-26, June 1979, pp. 980-986.

[8.5] K. M. Cham and S. Y. Chiang, "Device Design for the Submicrometer P-Channel FET with n+ Polysilicon Gate," IEEE Trans. Electron Devices, ED-31, July 1984, pp. 964-968.

[8.6] J. J. Barnes, K. Shimohigashi, and R. Dutton, "Short-Channel MOSFET's in the Punchthrough Current Mode," IEEE Trans. Electron Devices, ED-26, April 1979, pp. 446-453

[8.7] Y. A. EI-Mansy and R. A. Burghard, "Design Parameters of the Hi-C DRAM Cell," IEEE I. Solid-State Circuits, SC-17, Oct 1982, pp.951956.

[8.S] H. Katto, K. Okuyama, S. Megure, R. Nagai and S. Ikeda, "Hot Carrier Degradation Modes and Optimization of LDD MOSFET's," Tech. Digest ofIEDM 1984, pp. 774-777.

[8.9] S. Odanaka, M. Fukumoto, G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, "A New Half-Micrometer P-Channel MOSFET's with Efficient Punchthrough Stops," IEEE Trans. Electron Devices, ED-33, Mar. 1986, pp. 317-321.

Chapter 9

A Study ofLDD Device Structure Using 2-D Simulations

In this chapter, analysis and design of LDD (Lightly Doped Drain) devices using two-dimensional device simulation and experiments will be described to illustrate the usefulness and necessity of using computer-aided design tools in the fabrication of VLSI devices. First, the problem of high electric field in VLSI devices and the use of LDD device as a possible solution is discussed. The fabrication and simulation of LDD device is then described. Finally, the performance, characteristic, physics and design considerations of LDD device are presented in detail.

9.1 High Electric Field Problem in Submicron MOS Devices

In Very Large Scale Integrated (VLSI) circuits, the dimensions of devices are continually being scaled down to obtain higher density and speed. The channel length, junction depth and gate oxide thickness are scaled down while the channel doping is scaled up. These scalings are necessary to provide more current drive while maintaining the right device threshold voltage and low leakage current. However, the power supply voltage tends to remain unchanged due to system requirements. The same voltage is hence being applied to a

much shorter channel which results in a higher channel electric field. In addition, the shallower junction and thinner gate oxide also make the electric field at the drain junction higher. Eq. (9.1a,b) [9.1],[9.2] is a simple analytical expression relating the maximum drain electric field to device parameters.

where Em is the maximum drain electric field, VD is the applied drain voltage, VDSAT is the drain saturation voltage, Tox: is the gate oxide thickness,10 is the junction depth, L is the effective channel length and ESAT is the critical field for Velocity saturation and is about 3E4 V / cm.

It can be seen that as gate oxide thickness, junction depth and channel length are scaled down, the maximum drain electric field increases. Electrons in the channel are accelerated by this high drain electric field to reach high energy. These high energy electrons are called 'hot electrons' and they can cause device failure and long term reliability problems.

One problem is that some electrons can reach high enough energy to cross over the silicon/silicon dioxide barrier and create damage at the oxide/silicon interface. The interface damage can cause threshold voltage shift and also reduce the mobility of electrons. The current driving capability of the device is hence continually being degraded during device operation. This presents a severe reliability problem because circuit failure can occur after a certain period of operation. Another problem is that the high energy electrons can cause impact ionization in the drain depletion region, generating electron/hole pairs. The electrons are collected by the drain while the holes go into the substrate. The substrate hole current forward biases the source junction and electrons are injected into the substrate. These electrons will be collected at the drain as excess current and generate more impact ionization substrate current. This is a positive feedback mechanism which can cause the drain current to increase rapidly. The resulting avalanche breakdown will destroy the device. Excessive substrate current can also cause problems to substrate bias generation circuits and is a potential cause of latchup in CMOS

circuits. Eq. (9.2) [9.3] is an empirical analytical expression relating substrate current to maximum drain electric field.

m

where IDS is the drain current and Em is the maximum drain field.

New device structures are needed to reduce the drain electric field and hence prevent hot electron degradation and catastrophic drain breakdown. Several device structures have been proposed, such as lightly doped drain (LDD) device [9.4],[9.5] and As/P double diffused device [9.6]. The idea is to use a lightly doped region to drop off some drain voltage so that the drain electric field can be lowered. A more graded junction also helps to reduce drain electric field. In the design of such devices, a lot of issues need to be considered. Major concerns are whether the additional n- region will degrade device performance, what is the right doping concentration of the n- region to achieve both low electric field and acceptable series resistance, and whether low electric field leads to less hot electron related problems. In this chapter, only the LDD device will be discussed.

9.2 LDD Device Study

Lightly doped drain (LDD) device has received much attention in recent years as an important VLSI device. The major advantage of LDD device is that the lightly doped region can reduce the peak electric field at the drain. This results in higher breakdown voltage, lower substrate and hot electron currents and hence improved reliability. Other proposed advantages are reduction of short channel effect and improvement in punchthrough voltage due to the shallower tip junction. Experimental results on LDD device have been reported in several papers [9.4],[9.5]. However, the physics of submicron LDD device is not well understood. This is due to the complexity of two-dimensional device effects and difficulties in measuring and extracting parameters for submicron devices. In this section, the device physics for a half micron LDD device is investigated by using the two-dimensional device simulation program CADDET together with experimental results. The combination of computer

simulation and experimental analysis is found to provide important insights into the understanding of the LDD device in terms of breakdown, trapping, punchthrough and others. Simulation results are found to agree well with experiments.

Device Fabrication and Simulation

LDD device differs from conventional devices by having a n- region at both the source and drain side. Fig. 9.1 shows the conventional and LDD device respectively. Different processing methods can be used to create the LDD device structure. In our laboratory, a n- implant is done after the polysilicon gate is defined and etched. (The n- implant dose will be in unit of cm-2 throughout the chapter.) A thin oxide is grown after the implant and then a layer of oxide from 100 nm to 300 nm is deposited by low pressure chemical vapor deposition (LPCVD) at 9O<Y' C. This oxide layer is then anisotropically etched to form an oxide spacer at the polysilicon gate edge. Heavy dose Arsenic implant is then done to create the n+ source and drain junctions. Fig. 9.2 shows the processing sequence used to fabricate the LDD device. The device used in this work has gate oxide thickness of about 20 nm, a junction depth of about 0.25 micron and a n- region with various doping levels and lengths.

The two-dimensional simulation program CADDET used to study the LDD device solves both the Poisson equation and the current continuity equation simultaneously. The program does not have an impact ionization model and hence cannot simulate substrate current. However, since the substrate current is related to the maximum drain electric field (Eq. (9.2», very useful information can still be obtained. In CADDET, the n- region can only be placed either on the source or drain end. The tip is hence placed on the source side to study the effect of series resistance on device characteristics and on the drain side to study drain electric field effects. On the source side, the gate always covers the entire source region, while on the drain side, the overlap between gate and drain can be varied. Both the length of the n- region and its doping profile can be varied. The particular limitations of CADDET need to be taken into account in the interpretation of simulation results. Fig. 9.3 shows

CADDET SIMULATION

.,. DEPLETION -.:.:..

EDGE

1~________~________~________~______~

DRAIN

~u 0.6

e············- ..

DEPLETION ' EDGE

________ ________ ________L______

(micron)

Fig. 9.3. Structures used for source and drain simulations.

the structure used in simulating the source and drain side respectively. Note that the device channel widths used in the simulation is different from that in the experimental data. Therefore only the trend should be compared.

Performance Comparison Between LDD and Conventional Device

One common criterion used to evaluate a certain device technology is to plot the saturation current versus the punchthrough voltage for the devices. The idea is that the shorter the channel length, the higher is the current but at the same time, the lower is the punchthrough voltage. For the same channel length, a technology with a deeper junction will have lower punchthrough

voltage while one with lower source/drain doping and shallower junction depth (hence higher series resistance), will have lower saturation current. The saturation current versus punchthrough voltage characteristic tells us the best current drive we can get subject to a certain punchthrough voltage requirement and is hence a good evaluation of the performance of a technology. In simulating the performance comparison between LDD and conventional device, a 0.2 micron n- tip is placed at the source side. The n- dose and channel lengths are varied. For punchthrough simulation, the gate voltage is set at zero volt and the drain voltage is stepped in 0.1 volt increments. The punchthrough voltage is defined as the drain voltage at which the drain current is 10 nA per micron channel width. Saturation current is defined at VG = VD = 5 V. Fig. 9.4 shows a plot of the simulated saturation current versus punchthrough voltage characteristic. It can be seen that for the same punchthrough voltage, the saturation current of the LDD device is about the same or lower than conventional devices, depending on the dose of the n- region. Fig. 9.5 is a plot of I DSAT versus punchthrough characteristic from some experimental LDD and conventional devices, which agrees with the simulation. The reason for such inferior performance of LDD in the half micron device is due to the fact that the series resistance of the n- region is quite comparable to the channel resistance. The gain in punchthrough voltage due to the shallow n- junction is more than offset by the decrease in current due to the series resistance. Fig. 9.6 and 9.7 plots the simulated linear and saturation transconductance characteristic for conventional and LDD devices under different gate bias. The numbers in parenthesis are the effective channel lengths. In the linear region, the percentage degradation becomes worse with increasing gate voltage, whereas in the saturation region, degradation effect is less and decreases with increasing gate voltage. The experimental linear and saturation transconductance characteristics shown in Fig. 9.8 and 9.9 show the same trend. Since in CADDET, the n- region on the source side is entirely covered by the gate, the effective series resistance is reduced at high gate voltage and the degradation due to this resistance is being under estimated. However, CADDET does provide the right direction and saves a lot of time and effort in experimentation. The typical time required to fabricate and test the devices is about 2-3 months while the simulations can be done on a HP1000 minicomputer in a few days. Moreover,