Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

Chapter 8

Drain-Induced Barrier Lowering in Short

Channel Transistors

Drain-induced barrier lowering (DIBL) [8.1]-[8.6] has been studied by many workers. The result of DIBL is an increase in the residual leakage current in short channel devices as the drain to source voltage is increased. Fig. 8.1 shows the measurement of the drain to source current of a short channel MOSFET's, as a function of the drain bias, for gate bias of 0 V. Note that the current increases exponentially with drain bias. Fig. 8.2 shows the simulated potential profile between the source and drain of a long and short channel MOSFET's, with a drain to source bias of 9 V. The potential barrier between the source and the channel is lowered by the drain bias, for the short channel device. The drain to source leakage current is exponentially dependent on the potential barrier. This leakage current can cause many problems in circuits such as dynamic memories or low power circuits in battery operation environments. In the first example, if the pass transistor of the one-transistor dynamic memory cell [8.7] has significant leakage current, then the bit information of the cell may be lost. In the case of low power circuits, leakage current in the devices means much larger standby power. If severe leakage problems are present, the circuit may not function properly, especially for NMOS circuits. The design of analog circuits such as sense amplifiers in

memories depends on uniform device characteristics. DIBL effects can cause non-uniform device characteristics such as the threshold voltage variations. Also, in the case of dynamic logic design, severe leakage can cause the voltage at a node to drop, causing circuit malfunctions.

Since DIBL is of a major concern in the design of short channel transistors, simulations are always performed for the process and device design to make sure that DIBL is not significant, or that the amount of threshold voltage variation or residual leakage current is tolerable for the application. The simulations are performed by the combination of SUPREM, which simulates the impurity profiles, and GEMINI or PISCES, which simulate the DIBL effect for the device structure under study. The source/drain structure can have a significant effect on the DIBL characteristics. PISCES provides the highest degree of flexibility in the source/drain structure definition. Complicated structures such as LDD [8.8], n' pocket [8.9] can be defined in the PISCES input file. The GEMINI program, by itself, can have conventional or LDD structure. Higher degree of complexity is possible when the SUPRAGEMINI combination is used. However, the accuracy of the SUPRA program needs to be verified for the particular process under study. For simplicity, the following discussions will be mainly based on SUPREM-GEMINI simulations for n-channel devices with the conventional source/drain structure. Some examples of PISCES simulations will also be presented.

The term "punchthrough voltage" (VPT) is used to describe the drain voltage at which the channel current is equal to a specified value, when the gate is biased in the off state, usually at zero volt. Before looking into the dependence of the punchthrough voltage on various process and device parameters, it is illustrative to study the effect of the drain bias on the potential barrier between the source and drain using simulations. Fig. 8.3 shows a series of two-dimensional potential contour plots for increasing values of drain bias, for an effective channel length of 1 J.lm. The spread of the potential contours towards the source is clear in these figures as the drain bias is increased. For this device, the drain to source current is 1 nA for a width of 50 J.lm when the drain bias is 9 V. Since the GEMINI program solves only the Poisson equation and does not solve the continuity equation, the calculations are accurate only in a limited range of the current-voltage characteristics. Hence, DIBL

Fig. 8.6, together with the potential contours. The punchthrough current will flow along the path which contains the minimum potential barrier height. Conventionally, the term "saddle point" is referred to the point along the bulk current path where the potential is minimum or maximum for electron or hole respectively. (The "saddle" shape can be visualized by combining Figures 8.4, 8.5 and 8.6.)

In this particular case, according to the simulation results, the punchthrough path occurs at the surface, and the minimum electron potential occurs at x = 1.24j.£m (point A in Fig. 8.6) for a punchthrough current of 1 nA and device width of 50 j.£m. From here on, the term "punchthrough point" refers to the location of the minimum potential (maximum electron energy) along the punchthrough path. Fig. 8.7 compares the bird's-eye-view of the potential profile for long and short channel MOSFET's. The effect of the drain bias on the potential profile at the channel region is evident for the short channel dev-

Ice.

The IDS vs. VDS curves can provide physical insights into the DIBL behavior of short channel devices. Fig. 8.8 shows the test and simulated data of n-channel devices, with Leff = 0.5 j.£m. Log(IDs) is plotted versus VDS for two values of gate to source voltage (VGs), 0 V and 0.2 V. At high drain bias, the drain current increases rapidly and exponentially with the drain voltage in both cases. Also, the drain currents are approximately equal for the two different gate biases. At lower drain bias, the drain current is less dependent on the drain bias, especially for the case with gate bias of 0.2 V. Also, the dependence of the drain current on the gate bias increases. This behavior is due to a change in the punchthrough current path as drain bias increases. The slope is less steep at voltages less than 3 V. This is because the current path is along the surface. The dependence of IDS on VDS is expected to be weaker since the surface potential is mainly controlled by the gate bias. Surface punchthrough occurs before bulk punchthrough for the case of VGS = 0 V, due to the surface energy band bending, the combination of channel implants, and shallow junctions, producing a lower potential barrier at the surface. The change from surface punchthrough to bulk punchthrough can be more clearly seen for the case of VGS = 0.2 V. The dependence of the drain current on the gate bias is also expected to be large for surface punchthrough, as is confirmed

e-0.100

0..-0.150

Fig. 8.9. Potential profile vs. vertical distance for points (A) and

(B) in Fig. 8.8.

input file. Here the source is located between 0 and 1 p.m• .The parameter y indicates the distance of the punchthrough point measured from the silicon surface. This point changes from being at the surface to 0.77 p.m into the bulk for the drain bias increasing from 2 V to 5 V. This agrees with the previous discussions which concludes that surface punchthrough is occurring at point A and bulk punchthrough is occurring at point B. The potential profile as a function of the vertical distance from the surface into the substrate is plotted in Fig. 8.9, for the two bias points A and B. The horizontal distance from the source is chosen to be equal to the simulated horizontal position of the punchthrough point. The potential maximum (hence energy minimum for electrons)