Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

shows the determination of the "punchthrough voltage" VPT using 10 nA as a reference current, which is found to be 6.3 V for the device under study.

7.4 Relationship between Device Characteristics and Process Parameters

In this section, the relationship between device electrical characteristics and process parameters will be discussed. The relationship can best be understood by using a combination of experimental data and simulated data. Simulations allow one to observe the internal structure as well as the internal electrical condition of the device, hence allowing better understanding of the device characteristics. The dependence of the threshold voltage, subthreshold slope, and short channel effects on the channel implant parameters and device structures such as gate oxide thickness and junction depths are discussed. Transistors with channel length down to one micron will be discussed in this chapter, while submicron devices will be discussed in Chapter 12.

To understand the effect of channel implant on the device characteristics such as the threshold voltage, it is better to begin with a longer channel length, such that the correlations between the threshold voltage and implant parameters will not be complicated by significant short channel effects. The simulated threshold voltage as extrapolated from the subthreshold slope (see Fig. 7.13 and Eq. 7.6) for different channel implant profiles for the case ofLeff = 2.6 JJm and Weff = 48 JJm is shown in Fig. 7.16, together with test results from CMOS lots. No correction in the simulated threshold voltage is necessary since the correction is small at this channel length. The threshold voltages of the data have been normalized to an interface fixed charge density (Qss) of 2E10 cm-2, to be consistent with that used in the simulations. VDS and VBS are 3 and -1 V respectively. The gate oxide thickness is 35 nm. The horizontal axis indicates the channel implant parameters. The numbers (A,B) mean that the shallow implant (30 KeY) has a dose of AEll cm-2, and the deep implant (50 or 70 KeV) has a dose of BEll cm-2. The profiles are separated into two groups, one with a deep implant energy of 50 KeV, and the other of 70 KeV. The figure shows that the simulation and experiment agree well for a large range of

implant parameters. It also must be emphasized that in most cases, the comparison of experimental data and simulation data is meaningful only when there are significant statistics, due to process variations and measurement precision. From the figure, it can be seen that for the same implant energy, the threshold voltage increases with dose, as is expected. Also, the dependence of VT on the shallow implant dose and the deep implant dose are approximately equal. The increase in VT is approximately 0.1 V per 1Ellcm-2 increase in dose, with an accuracy of about 0.02 V. This is because the two doses are similar in magnitude (in contrast to thin oxide devices where the low energy dose is higher than the high energy dose; see Chapter 12), and also because the diffusion of the impurities during the fabrication process has smoothed out the distribution. Fig. 7.8 shows that for a channel boron implant of SEll cm-2 at 30 KeV and 4Ell cm-2 at 70 KeV, and with typical CMOS process temperature cycles, the impurity profile is almost Gaussian, instead of a two peaked structure.

The dependence of VT on channel profile is also studied for the case of short channel devices. Fig.7.17 shows the simulated threshold voltages, together with experimental data, for the same range of implant parameter values. The simulated threshold voltage is generated from the subthreshold slope simulation, using the SUPREM-GEMINI programs, then corrected for the deviation due to the GEMINI approximation. The agreement between experiment and simulation is quite good. The simulations show that the dependence of the threshold voltage on the implant dose is similar to the device with Leff = 2.5 J.'m.

The sensitivity of the threshold voltage to the substrate bias (the "body effect") can also be studied using simulations. Substrate bias can be applied to the device in the GEMINI program. The threshold voltage, under a desired drain bias, can then be calculated as a function of the substrate bias. Fig. 7.18 shows such a simulation, where the drain bias is at 3 V, for channel lengths of 2.5 J.'m and 1.1 J.'m. The results show that the threshold voltage rises rapidly during the first one volt of substrate bias and then rises at a slower rate with increasing substrate bias. This can be explained by the channel implant profile. As the substrate bias is increased, the depletion edge moves from the high impurity concentration region near the surface to the lower concentration

190 Computer-Aided Design

region deeper into the substrate. Since the body effect is proportional to the square root of the impurity concentration, the body effect is reduced at higher substrate bias. Another interesting result is that the device with short channel length has significantly less body effect. This can be explained by Fig. 7.19(a) and 7.19(b) where the 2-D potential contours and the depletion regions of the two devices are shown at a substrate bias of -1 V and drain bias of 3 V. The depletion region at the drain of the short channel device encroaches into the channel area. This causes an effective reduction of the channel impurity concentration, hence a lower body effect. Note that the channel depletion edge of the short channel device is deeper than that of the long channel one. Fig. 7.20 shows the experimental data for similar devices. The agreement between experiment and simulation is good.

The simulation of the threshold voltage versus Leff is also useful because it defines the appropriate channel length for a particular process. It also shows the sensitivity of the process and device design to short channel effects. The channel length should be chosen such that the sensitivity of the threshold voltage to the channel length is small, so that any variations in the channel length due to processing will not cause a serious variation in the threshold voltage. The physics of threshold voltage drop with reducing channel length has been discussed in many papers and will not be reproduced here [7.4],[7.23],[7.24]. The most simple explanation is the charge sharing model [7.23]. In this model, the depletion layer at the drain and source have consumed a significant fraction of the channel charge, thus effectively reducing the channel doping concentration. This is especially severe as the channel length decreases, and when the drain is under a large bias.

Fig. 7.21 shows the simulation of the threshold voltage of p-channel transistors as a function of effective (electrical) channel length, for a drain bias of -3.3 V. The SUPREM III and PISCES programs are used. The simulations show that for this particular process, the threshold voltage is not very sensitive to the channel length at IlJm, but is quite sensitive at 0.8 IJm.

The above discussions have emphasized the threshold and subthreshold regions of the transistor characteristics. In these regions, short channel effects such as subthreshold leakage and threshold sensitivity to channel length are very significant. The threshold voltage is a very important parameter because it influences the performance (current drive) and also the subthreshold leakage

of the device. Therefore, simulations in these regions are always necessary in VLSI device development to assure that the device will perform properly at the desired channel length. The full I-V characteristics of the transistor can be simulated by using the CADDET or PISCES programs. The reader is referred to Chapter 14.

[7.6] G. W. Taylor, "Subthreshold Conduction in MOSFET's," IEEE Trans. Electron Devices, ED-2S, March 1978, pp. 337-350.

[7.7] K. Yamaguchi, "A Mobility Model for Carriers in the MOS Inversion Layers," IEEE Trans. on Electron Devices, ED-30, pp.658-663, June 1983.

[7.8] Y. EI-Mansy, "MOS Device and Technology Constraints in VLSI,"

IEEE Trans. on Electron Devices, ED-29, Apr 1982, pp. 567-573.

[7.9] S. E. Laux and F. H. Gaensslen, "A Study of Avalanche Breakdown in Scaled n-MOSFET's," Tech. Digest ofIEDM 1984, pp. 84-86.

[7.20] R. R. Troutman, "Ion-Implanted Threshold Tailoring for Insulated Gate Field-Effect Transistors," IEEE Trans. Electron Devices, ED-24, Mar 1977, pp. 182-192.

[7.21] H.-G. Lee, S.-Y. Oh and G. Fuller, "A Simple and Accurate Method to Measure the Threshold Voltage of an Enhancement-Mode MOSFET,"

IEEE Trans. Electron Devices, ED-29, Feb. 1982, pp. 346-348.

[7.22] S. Odanaka, M. Fukumoto, G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, "A New Half-Micrometer P-Channel MOSFET with Efficient Punchthrough Stops," IEEE Trans. Electron Devices, ED-33, Mar. 1986, pp. 317-321. 317-321. 317-321.

[7.23] P. K. Chatterjee and J. E. Leiss, "An Analytic Charge-Sharing Predictor Model for Submicron MOSFET's," Tech. Digest of IEDM 1980, pp. 2833.

[7.24] K. Yokoyama et al., "Threshold-Sensitivity Minimization of ShortChannel MOSFET's by Computer Simulation," IEEE Trans. Electron Devices, ED-27, Aug 1980, pp. 1509-1514.