Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

approach to provide a preliminary set of data even for short channels, since it is often possible to make rough corrections on the long channel threshold voltage to provide an estimate of the short channel threshold voltage.

The GEMINI program has the next higher level of complexity. It solves the two-dimensional (2-D) Poisson equation and generates device parameters such as the subthreshold slope. In the case of short channel devices, where the threshold is very sensitive to the channel length and drain bias, it is necessary to use this program to calculate the threshold voltage. In this case, twodimensional effects are dominant, with the drain bias affecting the potential

........

(MICRONS)

Fig. 7.7. Simulation of an n-channel MOSFET with channel length of 1.2p,m. The gate and drain bias are 0 and 3 V respectively.

barrier between the source and drain. Fig. 7.7 shows a simulation of a short channel transistor with a drain bias of 3 V. The depletion region at the drain extends into the channel area. This shows clearly that 2-D simulation is absolutely essential. The GEMINI program can provide a reasonable approximation of the channel, source and drain profiles, using Gaussian distributions.

The third degree of complexity is the combination of SUPREM II and GEMINI, which provides accurate vertical impurity profiles for the channel and the source/drain, during the device simulation. In this case, the channel

and source/drain profiles are more realistic, since they are typically not Gaussian. For example, in short channel devices, a combination of shallow and deep implants is used to set the threshold voltage as well as the punchthrough voltage. Also, the source and drain profiles may be much steeper than a Gaussian profile, due to the thermal diffusion properties of the impurities, which depends on the impurity concentrations [7.18]. Fig. 7.8 and Fig. 7.9 show typical channel and source/drain profiles respectively, as simulated by SUPREM II. The source/drain impurity profile may not affect the threshold voltage simulation significantly, but will affect the DIBL and hot electron effect simulations.

The fourth degree of complexity is the combination of SUPRA and GEMINI, which provides not only the vertical impurity profile, but also the horizontal distribution at the source/drain. This is essential if one wants to simulate source/drain structures that are more complicated, such as the LDD [7.11] structure. SUPRA also allows one to simulate isolation structures, with certain limitations, and couple that structure to GEMINI for device simulations. This is useful for the simulation of narrow width effects or for the simulation of field parasitic transistors with advanced field isolation structures. For more complicated isolation structures such as SWAMI [7.19], it is necessary to couple the SOAP, SUPRA, and GEMINI programs to simulate the narrow width effects.

The CADDET program is used when it is necessary to investigate the full I -V characteristics of the device. The program does not accept SUPREM or SUPRA output files. Hence it is not as accurate as the SUPREMGEMINI or SUPRA-GEMINI combinations in the simulation of the threshold voltage, unless the profiles are carefully specified by first running the SUPREM program and then approximating the profile with a Gaussian distribution. The applications of this program are described in Chapter 3, 9 and 14. The PISCES program is a two-dimensional, two carrier semiconductor device modeling program, which can simulate device characteristics under steady state or transient conditions. The program, when coupled with SUPREM III, provides much larger flexibility in the device structure as well as solution accuracy compared with the GEMINI and CADDET programs. The program is useful ill simulating both the subthreshold and I-V characteristics of

transistors, as well as transient behaviors such as latchup. The disadvantage of PISCES is longer CPU time. The issue of CPU time is becoming less important as computer hardware improves continually. Also, the input file for PISCES can be simplified by using macro commands. Examples of PISCES applications will be presented in Chapters 3, 7, 8, 12, and 13. The coupling of PISCES and a 2-D process simulator such as SUPREM IV (being .developed at Stanford University) offers the potential for the highest degree of accuracy and flexibility in the device simulation, provided that the individual programs have been verified.

7.3 Methods Of Generating Basic Device Parameters

In this section, methods of generating basic device parameters will be presented. Threshold voltage, subthreshold slope and punchthrough voltage will be simulated using different techniques. The assumptions used by the different programs will be discussed, so that the users are aware of the approximations being applied.

The first example is the simulation of the threshold voltage using the SUPREM program. In this case, the threshold voltage will correspond to the MOS capacitor threshold, which is very close to the long channel MOSFET threshold measured by the current versus gate voltage method. The model used is based on the full depletion approximation and the assumption of quasi-neutral impurity profiles [7.20]. The user inputs the process steps for the MOS structure. The program then calculates the impurity profile, and the threshold voltage as a function of the substrate bias. Fig. 7.10 shows the curve of simulated threshold voltages for p-channel transistors as a function of the counter-doping implant dose, together with experimental data. Good agreement is observed. This method of simulating the threshold voltage has the advantage of being the most simple, and the least time consuming. The limitation is that the threshold corresponds to the long channel threshold. This program is useful when one wants to look at the dependence of threshold voltage on the impurity profile without the complication of the short channel effects.

-1.1 _ ----------------- _

--- SIMULATION (SUPREMI

... C-v

• LONG CHANNEL MOSFET

>~... -1.0

COUNTER-DOPING DOSE (X10" em-Z '

Fig. 7.10. Simulation of p-channel threshold voltage vs. counterdoping dose.

If the threshold voltage of a short channel transistor is to be simulated, then two-dimensional numerical analysis is necessary to provide good accuracy. The combination of SUPREM and GEMINI in most cases provides sufficient accuracy. The channel and source/drain implant profiles are first simulated by the SUPREM program. The structure of the transistor is defined by the GEMINI program. The impurity profiles at the channel and source/drain area are provided by the SUPREM data file after the SUPREM simulation is completed. Fig. 7.11 shows the bird's-eye-view of the impurity profile generated by the GEMINI program using the SUPREM data. The source/drain and channel profiles are displayed very clearly. The GEMINI program then solves Poisson's equation based on those profiles and bias conditions. It is important to know the threshold voltage of a short channel device biased at the power supply voltage VDD , since this is the condition at which the device is biased when it is in the off state in an inverter circuit. For large drain bias, short channel effects are very significant and device characteristics have to be determined by 2-D simulations. The GEMINI program simulates the subthreshold characteristics of the transistor under this bias condition by

calculating the drain to source current versus gate bias, from which the subthreshold slope and threshold voltage can be extracted.

The GEMINI program solves Poisson's equation within the device structure and generates the potential profile. Fig. 7.12 shows the bird's-eye- view of the potential profile within the device structure. The effect of the drain bias in lowering the potential barrier can be observed qualitatively. In the GEMINI program, the quasi-Fermi level at the channel region is set equal to that of the drain bias. Hence under a large drain bias, the program underestimates the inversion charge after the device is turned on, and overestimates the band bending. The subthreshold current will continue to increase exponentially even after the threshold voltage is reached. Fig. 7.13 shows the simulation of the subthreshold characteristics of an-channel MOSFET, together with the experimental data. The simulated data begins to deviate from the experimental data at high current levels, hence precautions need to be taken when interpreting the simulation results. It is useful to define a threshold current, from which the threshold voltage can be extracted. The conventional value of the threshold current is given by [7.21]

where Leff and Weff are the effective channel length and channel width respectively. If this value of threshold current is used, then the simulated threshold voltage will be too low, due to the deviation from experimental data at turn-on. This deviation is reduced for longer channel lengths. For example, at Leff = 2.5p.m, the correction in the simulated threshold voltage is 0.03 V. In order to be consistent with experiment, it would be necessary to include this correction factor for short channel transistors. Another method would be to use a lower value for the threshold current during measurement. Taking the correction into account, the agreement between experiment and simulation is very good over a wide range of implant doses and energies (see Fig. 7.16 and 7.17 in section 4). The subthreshold slope can also be calculated from this simulation by taking the inverse slope of the 10g(IDs) versus VGS curve.

A more accurate method of simulating the subthreshold slope and threshold voltage of short channel devices is to use the PISCES and SUPREM III programs. The solution is valid for the entire range of bias conditions applicable to the device. Fig. 7.14 shows the result of a subthreshold simulation. The

agreement is good from subthreshold to beyond threshold. The compromise is longer CPU time.

Although the SUPREM II-GEMINI combination is sufficient for many applications, sometimes it is necessary to simulate characteristics of devices with complicated source/drain or isolation structures. Examples are subthreshold leakage of p-channel transistor with n- pocket [7.22] (see Chapter 13) and narrow width effects of LOCOS and SWAMI isolations (see Chapter 11). In these cases, the SUPREM III-PISCES or the SUPRA-GEMINI combination are needed.

In the design of short channel transistors, a major concern is the problem of "punchthrough", or more accurately, drain-induced barrier lowering (DIBL) [7.4]. The bias applied at the drain of the transistor has the effect of lowering the potential barrier between the source and the drain. "Punchthrough" traditionally means that the drain and source depletion regions are merged, and the maximum potential barrier to carriers is less than the junction "built-in" voltage. In this case, the bias at the drain can affect the potential distribution at the source. But the leakage current may still be negligible until the drain bias has caused significant lowering of the potential barrier height between the source and the channel. Since the diffusion current between the source and the drain is exponentially proportional to this barrier, the leakage current is very sensitive to the drain bias at short channels. The detailed physics of DIBL will be discussed in Chapter 8. Since leakage current is a major concern for low power operation, the DIBL effect is always simulated during process development. (This is especially important for VLSI device development where channel length is one micron or less.) This can be accomplished by using a combination of process simulator and device simulator. The process simulator generates the channel and source/drain profiles, and the device simulator simulates the DIBL effect as a function of the drain bias. Fig. 7.15 shows the simulated data of leakage current at zero gate bias vs. the drain bias, for an n-channel transistor with channel length of 0.6 JJm using the SUPREM II and GEMINI programs. It is useful to define a "punchthrough voltage", which can be defined as the drain bias at which a certain level of drain current (punchthrough current) is observed at zero gate bias. The definition of this current level would depend on the application of the devices. Fig. 7.15