Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

Here dx/dt is the oxide growth rate. A, A/B and K are all singly activated functions of temperature. The prediction of the default parameters for 850°C is shown in Fig. 6.2. Obviously the parameters in this model need some modification to play-back the measurements. Also the initial oxide thicknesses must be introduced artificially. The solid lines in Fig. 6.2 result form the following set of parameters.

2.8nm 850°C

3.4nm 900°C

4.0nm 950°C

5.5nm 1000 °C

The fit to the measurements is quite good. Here the linear rate coefficients are the same as the default values in SUPREMo However the value ofL the parameters in K are significantly different from the default values.

For these calculations, the initial oxide thickness (Fig. 6.2) was deposited prior to the oxidation. This is not always desirable. An example is the gate oxidation in a typical CMOS process. This oxidation is usually done immediately after the shallow channel boron (or blanket) implant. This implant adjusts the threshold for both the n and p-channel devices. During the gate oxidation it is important to correctly model the incorporation of boron into the gate oxide (see section 6.4). Thus the entire oxide should be grown rather than depositing the first few nanometers. For this case the initial oxidation cycle can be lengthened to provide the initial oxide. For example, the coefficients listed above yield 2.8 nm in 12 minutes at 850°C. Thus any 850 °C dry oxidation on

bare silicon can be lengthened by 12 minutes to provide the initial oxide thickness. This slight additional thermal cycle will have very little effect on the resulting boron profile.

6.4 Oxygen Enhanced Diffusion of Boron

For low temperature oxidations, the diffusion constant for boron is dominated by the contribution from oxygen enhanced diffusion (OED) [6.11-6.20]. This is quite important for advanced CMOS processes. The gate oxide is usually grown after the shallow boron channel (or blanket) implant. This implant must be shallow to control leakage in the p-channel device. A significant fraction of the channel implant is "sucked up" into the gate oxide as it is grown. This boron is inactive in the gate oxide and does not contribute to the threshold adjustment. It is very important that the simulation predict the correct amount of boron remaining in the silicon after the gate oxidation or else the predicted threshold voltages will be incorrect.

The flow of boron into the gate oxide is controlled primarily by two parameters: the segregation constant (m) for the silicon/oxide interface and the diffusion constant (D) for boron during the gate oxidation (see sec. 2.2). The segregation constant and diffusion constant are determined by the following equations and parameters. Here the segregation constant is the ratio of the equilibrium dopant concentration in the oxide to that in the silicon.

An experimental n-well CMOS process was developed at Hewlett Packard Laboratories using a 25 nm gate oxide grown at 850°C. At this temperature

.10E+18Lo Concentration (crn-3)

JOE +17

Fig. 6.3. SUPREM III Simulation of Channel Doping Profile of

P-channel Transistor. This graph compares the predicted channel profile for two values of the parameter liiO' The

segregation constant was 10 for each simulation.

the boron diffusion constant is dominated by the contribution from OED. Fig. 6.3 shows the simulated channel doping profile in the p-channel device for two values of the parameter /uo which is a dimensionless parameter defined differently for each dopant species. The parameter liiE is kept at its default value (0.57 eV). It is clear from Fig. 6.3 that the predicted channel doping profile is quite sensitive to the value of the OED parameters.

Fig. 6.4 shows the fraction of the channel boron implant that migrates to the gate oxide as a function of Iii. One curve in Fig 6.4 uses the default segregation constant m which is about 10 at 850 DC. The other curve fixes m at a value of 3.

Fig. 6.5 shows how the long-channel extrapolated threshold voltage for the n and p-channel device varies with liiO. Here the threshold voltages were

calculated by three techniques. One of these used the electrical parameter extraction features of the SUPREM III program. In this mode, SUPREM solves the one-dimensional Poisson equation for a given gate and substrate

40Boron Content of Gate Oxide (%)

25nm Gate Oxide

Grown at 850C

30

20

10

Fig. 6.4. Boron Content of Gate Oxide. This plot shows the fraction of the shallow channel boron implant that is incorporated into the gate oxide as a function of the parameter IuD for two values of the segregation constant m.

bias. From this, the channel charge is calculated as function of gate bias. Plotting channel charge versus gate bias allows one to determine the extrapolated threshold voltage.

The other two curves in Fig. 6.5 were obtained from the device simulation program PISCES lIB. PISCES lIB is used to calculate the drain current for each gate bias. The extrapolated threshold is then obtained in the usual way. In one curve, a constant carrier mobility was used. In the other, a field dependent mobility was specified (see Section 3.3). The constant mobility threshold voltages agree well with the threshold voltages from SUPREMo The field dependent mobility changes the shape of the drain current versus gate bias curve. This shifts the extrapolated threshold to a slightly lower voltage. It is these values that should be compared to measurements which are also influenced by the field dependence of the carrier mobility.

It is obvious from Fig. 6.5 that the values chosen for the OED parameters and the segregation constant have a significant effect on the predicted

1.8Threshold Volta e (Absolute Value) M

--Measured

1.6- - Simulated

1.4

Long Channel

Threshold Voltage

f··"O = 0

m = 10 (at 850C)

'~~----~1----~2-----+3----~4----~5

Substrate Bias (Absolute Value) M

Fig. 6.6. Long Channel Threshold Voltage versus Substrate Bias. The simulated threshold voltages were calculated with SUPREM III doping profiles in the PISCES lIB device simulator using the field dependent mobility model. For both the measured and simulated cases, the threshold voltage was extrapolated from the linear region of the I D versus VG curve at low drain bias.

threshold voltages. The measured nominal extrapolated threshold voltages for this process are 0.77 V for the n-channel device and -0.88 V for the p-channel. Only the threshold voltages simulated using the field dependent mobility model in PISCES should be compared directly to the measured values. For the range of segregation constant between 3 and 10 in Fig. 6.5, there is a range of fuo that would predict the correct threshold voltages. This range is approximately 1 ~liiO ~ 2 which is significantly different from the default value of 4.1. A reasonably good choice is to use m =10 and liiO =1. The resulting profile predicts the correct dependence of threshold on substrate bias as shown in Fig. 6.6. This indicates that the simulated channel profile is probably a good representation of the actual profile.

6.5 Shallow Junctions

In advanced MOS processes, the source/drain junction depth becomes an important parameter. Short channel effects are sensitive to this parameter. Shallow junctions are usually made by implanting arsenic (n+) [6.22] or BF2 (p+) [6.3] and annealing at relatively low temperatures (850 DC to 950 DC) in inert or dry ambient. For inert ambient anneals, the n+ or p+ profile is determined predominantly by concentration enhanced diffusion (CED) effects. This is modeled in SUPREM III by letting the diffusion constant be a function of the local free carrier density (see Eqs. (2.20) and (2.21» which depends on the doping density. This causes a high concentration arsenic or boron profile to diffuse more quickly than a low concentration profile.

Figs. 6.7 and 6.8 compare SUPREM III profiles with measured profiles for some typical source/drain implants and anneals. In general the agreement is quite good. This is usually true for arsenic and boron (BF2 implanted) profiles. Thus the models and parameters for CED of boron and arsenic appear to be reasonably accurate.

The situation is not as good for phosphorus. The diffusion of phosphorus in heavily doped silicon has always posed problems for simulation and our understanding is still incomplete. This arises in advanced MOS processes for "double diffused" junctions. Here a high dose of arsenic and a lower dose of phosphorus are implanted to form the n+ drain. This produces a more graded junction than arsenic alone, thus reducing the electric field at high drain bias (see Chapter 12). Our experience indicates that the models in SUPREM for phosphorus diffusion are not reliable for predicting the correct profiles for shallow double diffused junctions. Usually the simulated profile is shallower than the actual profile.

References

[6.1] H. Ryssel, et al, "Range Parameters of Boron Implanted into Silicon,"

Appl. Phys. 24, 1981 , pp. 39-43.

164 Computer-Aided Design

[6.2] M. Simard-Normandin and C. Slaby, "Empirical Modeling of Low Energy Boron Implants into Silicon," J. Electrochem. Soc. 132(9).1985, pp.2218-2223.

[6.3] R.G. Wilson, "Boron, Fluorine, and Carrier Profiles for B and BF2 Implants into Crystalline and Amorphous Si," J. Appl. Phys. 54(12), 1983,pp.6879-6889.

[6.4] A.E. Michel, et al, "Channeling in Low Energy Boron Ion Implantation," Appl. Phys. Lett. 44(4), 1984, pp. 404-406.

[6.5] F. Jahnel, et al, "Description of Arsenic and Boron Profiles Implanted in Si02, Si3N4 and Si Using Pearson Distributions with Four Moments," Nucl.lnstrum. and Methods (Netherlands) 182/183, 1981, pp. 223-229.

[6.6] YJ. Van der Meulen, "Kinetics of Thermal Growth of Ultra-Thin Layers of Si02 on Silicon, Part 1. Experiment," J. Electrochem. Soc., 119,1972, p. 530.

[6.7] R. Ghez and YJ. Van der Meulen, "Kinetics of Thermal Growth of Ultra-Thin Layers of Si02 on Silicon, Part 2. Theory," J. Electrochem. Soc., 119, 1972, p. 1100.

[6.8] EA. Irene, "Silicon Oxidation Studies: Some Aspects of the Initial Oxide Regime," Appl. Phys. Lett. 33, 1978, p. 424.

[6.9) G.F. Derbenwick and R.E. Anderson, "Rapid Initial Thermal Oxidation of Silicon," 1. Electrochem. Soc., 1983.

[6.10] H.Z. Massoud, "Thermal Oxidation of Silicon in Dry Oxygen - Growth and Charge Characterization in the Thin Regime," Stanford Electronics Laboratories, TR G502-1, Stanford University, Stanford Calif., 1983.

[6.11] DA. Antoniadis, A.M. Lin, and R.W. Dutton, "Oxidation-Enhanced Diffusion of Arsenic and Phosphorus in Near-Intrinsic (100) Silicon,"

Appl. Phys. Lett. 33, 1978, p. 1030.

[6.12] K. Taniguchi, K. Kurosawa, and M. Kashiwagi, "Oxidation Enhanced Diffusion of Boron and Phosphorus in (100) Silicon," J. Electrochem.