Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988

In most cases, however, the coupling coefficients bij and c are smaller than the coefficients aj, hence making the problem much simpler. As a first approximation, the parameters Dc, Ec , and Dw can be assumed to be linearly independent variables. The dependence of the threshold voltage can thus be expressed as:

(5.2)

In this case, four calculations only will be needed to determine the three coefficients a;'s, while it will take seven calculations to solve for all coefficients in Eq. (5.1). Therefore, there is significant savings in CPU time. The saving becomes more significant as the number of process parameters increases.

3)In most cases, and especially in the early stages of experiments, the trend rather than exact values generated by simulations should be emphasized. For example, in the above mentioned experiment on the threshold voltage, it would be a bad idea to try to generate the dose and energy that would give a threshold value of exactly -0.7 V. There are two reasons for this; first, the simulation tools are not always very accurate. The accuracy depends on the particular structure being considered and the simulation tools being used. Second, there are process control variations during fabrication, such as the line width and dielectric thickness variations. In VLSI, device performance is very sensitive to structural dimensions, so it is very important to understand the sensitivities. The simulations provide an optimized range of parameters for experimentation, which then provides feedback on the accuracy of the simulations. Through this feedback loop, the optimized process can be developed.

4)The simplest approach should be used in the simulations. It is a waste of time to simulate a structure with more accuracy than is necessary. For example, if one wants to calculate the threshold voltage of a long channel MOSFET, it is only necessary to use the SUPREM program, which considers the threshold voltage from a MOS capacitor point of view [5.3]. This method is valid because short channel effects such as drain-induced barrier lowering [5.4] are absent in this case. It would be a waste of time to use two-dimensional numerical programs in this case. There may be cases in which only rough estimates are needed to evaluate whether a particular idea

is feasible. In such a case, the simplest procedures that satisfy the relaxed accuracy requirements should be used. When the idea is considered feasible, and more detailed study is desired, then more sophisticated simulation tools will be used. Also, as mentioned in discussion 1), the simplest procedure usually provides the most basic and easily understood physical insight of the problem. In general, the idea is to choose the tool that provides the necessary accuracy, but not more.

5.2 Outline of the case studies

The following chapters are case studies in which simulations are used in VLSI device development. In Chapter 6, we present the application of SUPREM III in process development. The accuracy of the program is improved by adjusting the model parameters to fit experimental data. In Chapter 7, we discuss basic device physics for process engineers, and how to generate device parameters by using simulations. The relationship between device characteristics and process parameters are presented. Chapter 8 studies the drain-induced barrier lowering effect in shot channel MOSFET's. In Chapter 9, a combination of simulations and experiments are used to study in detail the lightly-doped drain (LDD) structure. The physics of the structure are revealed through simulations. Chapter 10 presents the use of CAD tools in analyzing a special structure, which is the trench isolation in CMOS. This chapter shows how simulations have identified a potential problem, and provided recommendations on how to minimize such problem. Chapter 11 shows the use of simulation tools in the development of new isolation structures such as SWAMI. Simulations are used to evaluate the performance of isolation structures. Chapter 12 presents how CAD is used in submicron CMOS transistor design. The issues of subthreshold leakage and drain-induced barrier lowering, as well as other concerns in short channel MOSFET's are discussed. Chapter 13 presents a methodology to systematically optimize a p-channel MOSFET with n- pockets, using PISCES simulations. Chapter 14 shows how simulations can be used to optimize the scaling of a process to achieve higher circuit performance and minimize process

complexity. Chapter 15 presents the simulation of parasitics in circuits. Parasitic resistances and capacitances are simulated in 2-D and 3-D, which provide very important information essential for circuit simulations. The physics of parasitic capacitances is also discussed.

References

[5.1] K. M. Cham and S. Y. Chiang, "Device Design for the Submicrometer P-Channel PET with n+ Polysilicon Gate," IEEE Trans. on Electron Devices, ED-31, July 1984, pp. 964-968.

[5.2] G. E. P. Box, W. G. Hunter, and J. S. Hunter, Statistics for Experimenters, NY:John Wiley & Sons, 1978.

[5.3] S. M. Sze, Physics of Semiconductor Devices, -zut ed., NY:Wiley Interscience, 1981.

[5.4] R. R. Troutman, "VLSI Limitations from Drain-Induced Barrier Lowering," Trans. on Electron Devices, ED-27, April 1979, pp.461468.

Chapter 6

SUPREM III Application

6.1 Introduction

SUPREM III has emerged as the most widely used process simulator. The authors of SUPREM III have attempted to include the most up-to-date physically based process models that are currently available and suitable for computer simulation. Innumerable research hours have gone into the development of the various models and fitting parameters. However a silicon process, whether it is bipolar, NMOS, or CMOS, is an extremely complicated entity. There are several problems inherent in the SUPREM process models.

1.All models are based on a limited data set. It would be impossible to accumulate data for the countless different combinations of process conditions that are currently used or may be used in the future. One should be especially careful when using SUPREM to make predictions for process steps that lie outside the range of the measured data used to formulate the process models. This has implications for shallow junctions, thin oxides and low temperature diffusion. All of which are important in advanced processes.

2.The data used to develop the process models is usually derived from carefully controlled experiments involving a small number of process steps.

However, in a real process, the many different process steps may interact with each other and produce unexpected results.

3.The models used in SUPREM III are physically based. Therefore interpolation between data points, where the same physics applies, should be acceptable. However it is possible that the process models are not based on complete or correct physical understanding. In this case, extrapolation between data points may not be accurate and slightly different process steps may produce unexpected results.

4.SUPREM III is inherently one-dimensional. However, as process dimensions shrink, two-dimensional effects become important. Therefore the dopant distribution in one area of the device structure becomes a function of the conditions present in adjacent regions (see Fig. 2.1). This is especially true for oxidation and diffusion which affect the point defect concentrations in adjacent semiconductor regions. The point defect concentrations then affect the diffusion processes in the adjacent regions.

For all the above reasons, the program user should have a healthy scepticism of the predictions from SUPREMo One should put confidence in the results only after they have been bench-marked against measurements, both electrical and analytical.

Typically, one is interested in predicting a particular set of electrical parameters for a particular process or class of processes. This set of electrical parameters may be very sensitive to some subset of the process steps. For example, MOS device parameters are very sensitive to the channel doping profile, gate oxide thickness and source/drain profiles. Latch-up, in a CMOS process, is most sensitive to the n-well and/or p-well profiles, and the substrate or epi doping. Bipolar device performance is most sensitive to the base doping profile. In each of these cases, a different set of process models have the most influence on the predicted electrical parameters.

In this chapter, we present some examples of the limitations of the process models in SUPREM that have been encountered in modeling device characteristics for CMOS processes. Suggestions are made on how to work around these limitations. Similar examples could be found for other sets of electrical parameters.

6.2 Boron Implant Prof"Iles

SUPREM III uses the Pearson IV profile type for all implant profiles unless a different function is specified. In general the Pearson IV profile can do a good job of fitting measured implant profiles. However, boron implants into single crystal silicon produce relatively complex profile shapes [6.1-6.5]. Most of the problem is due to channeling where the implanted ions follow open corridors through the crystal array. This produces a long "tail" on the implant. The situation is further complicated since the exact nature of the profile is sensitive to the implant angle and to the rotation of the wafer about the implant angle.

Fig. 6.1 shows a measured boron implant profile for 30 KeV at ~ implant angle. The dashed line in this figure is one attempt to fit a Pearson IV profile to the implant profile. The fit is fairly good for the upper two orders of

.10E+21Concentration (cm-3)

30 keV Boron Implant

.10E+20

.10E +18~.0-""""'~.1"""-~.2~-"".~3--.........~.4-........-!.5 Distance (um)

Fig. 6.1. Pearson IV Profile Fitted to a Measured Boron Implant Profile. The measured profile is from SIMS.

magnitude. However the measured and implanted profiles diverge at lower doping levels. Therefore this particular Pearson IV profile would work well for a channel implant where only the top two orders of magnitude are important. However, it would be very poor for a source/drain implant where the top five orders of magnitude are important. The Pearson IV profile would predict an excessive junction depth. Therefore one must be very careful using published Pearson IV coefficients since the fit may not be appropriate for all applications.

If one wished to represent the doping profile in Fig. 6.1 over a wider range of doping, a exponential tail on the profile would fit better than the Pearson IV. However, the Pearson IV profile with exponential tail is not an option supported by SUPREM III. Fig. 2.2 shows a comparison between the Pearson IV and Pearson IV with exponential tail.

6.3 Thin Oxide Growth

The growth of thin oxides is one of the most difficult aspects of IC processing to model [6.6-6.9). The growth of the first 7 om of oxide is very dependent on pre-oxidation cleans, the ambient present as the wafers are pushed into the furnace, pre-heat cycles, etc. Fig. 6.2 shows some data taken at Hewlett-Packard Laboratories for thin oxide growth at temperatures from 850 DC to 1000 DC in dry oxygen ambient. At least two effects are displayed in this data.

1.There is an apparent initial oxide thickness that is present even for "zero" time oxidation cycles. The log/log plot in Fig. 6.2a shows this effect. This initial oxide layer may result from the pre-oxidation clean and oxide growth during the wafer push.

2.An enhanced growth rate is present for thin oxides. This is easily observed when the data is presented on a linear/linear scale as in Fig. 6.2b. The slope of the thickness versus time plot is larger for thin oxides.

SUPREM III models the enhanced growth rate of thin oxides with the the following equation.