Книги2 / 1988 Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin (auth.) Computer-Aided Design and VLSI Device Development 1988
.pdfDevice Simulation |
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First, the mesh file is read using a mesh statement. The solution file is read using a load statement. Flags for the plots of the boundary, metallurgical junction, and depletion boundary are set in the plot.2d statement. In the contour statement, the variable for the contour plot is given as potential. The minimum (min), maximum (max), and increment (del) of the contour are also specified. The resulting contour plot is shown in Fig. 3.30. The contour plot gives a good overview of the 2-0 nature of the distribution.
The input of 1-0 cross-sectional plot of doping along and vertical to the channel is given below.
title plot 1-D cross-sectional plot of doping: n4pl.i
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$ load the mesh and solution nIes |
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innIe=n4msh3 |
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innIe=n4slv1 |
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x.s=O.O y.s=O.O x.e=3.0 y.e=O.O pause |
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The mesh and solution files are read first as in the previous example. In the plot.1d statement, doping (doping) is specified as a plot variable and absolute and logarithm parameters are set to plot the logarithm of the absolute value of doping density. Thus, the ranges of doping (min, max) are given from 10 (1010 em-3) to 20 (l(fO cm-3). For a log plot, min and max are the value of the base 10 logarithm. There are two plots in the example. In the first 1-0 plot, The cross-section statement is along the surface channel. The coordinates of the starting point (x.s, y.s) is (0.0,0.0) and that of the ending point (x.e, y.e) is (3.0, 0.0). As mentioned before, the origin of the coordinate system is at the
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Fig.3.31. (a) 1-0 plot of doping profile along the surface channel.
(b) 1-0 plot of vertical doping profile in the middle of the channel.
Device Simulation |
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upper left corner of substrate. The positive x direction is from left to right. The positive y direction is from top to bottom. The cross-sectional plot of doping along the surface channel is shown in Fig. 3.31(a). The second plot is along a vertical slice in the middle of the channel. The coordinates of the starting and ending points are (1.5,0.0) and (1.5,1.0). The plot is shown in Fig. 3.31(b).
As shown above, the graphical post processing is very important. It should be used to check the simulation structure to ensure correct dimensions and doping profiles. Second, useful device parameters such as a threshold voltage can be extracted from the I-V characteristics. Third, plots of internal distributions will help to understand the device operation and terminal characteristics. In the above example, the plot of doping profile is usually done to check that the transfer of doping from the SUPREM-III files is correct. Other usages of the graphical post-processing will be given in the second part of this book.
References
[3.1] J. A. Greenfield and R. W. Dutton, "Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation," IEEE Trans. on Electron Devices, ED-27, Aug 1980, pp. 1520-1532.
[3.2] S. Ogora, P. J. Tsang, W. W. Walker, D. L. Chritchlow, and J. F. Shepard, "Design Characteristics of the Lightly Doped Drain-Source (LDD) IGFET," IEEE Trans. on Electron Devices, ED-27, Aug 1980, pp. 1359-1367.
[3.3] R. D. Rung, H. Momose, Y. Nagakubo, "Deep Trench Isolated CMOS Devices," Tech. Digest of IEDM 1982, pp. 237-240.
[3.4] K. M. Cham, S. Y. Chiang, D. Wenocur, and R. D. Rung, "Characterization and Modeling of the Trench Surface Inversion Problem for the Trench Isolated CMOS Technology," Tech. Digest of IEDM 1983, pp. 23-26.
[3.5] R. S. Verga, Matrix Iterative Analysis, Englewood Cliffs, NJ:PrenticeHall, 1962, ch.6.
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[3.6] |
J.M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear |
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Equation in Several Variables, New York:Academic Press, 1970, pp. |
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214-230. |
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[3.7] |
T. Toyabe, "CADDET User's Manuaf', Hitachi Central Laboratories |
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[3.8] |
M. S. Mock, ''Analysis of Mathematical |
Models of Semiconductor |
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Devices, "Boole Press, Dublin, 1983. |
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[3.9] D. Vandorpe, J. Borel, G. Merke~ and |
P. Saintot, "Accurate Two- |
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Dimensional Numerical Analysis of the MOS Transistor," Solid State |
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Electronics, 1972, Vol. 15, PP. 547-557. |
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[3.10] H. L. Stone, "Iterative Solution of Implicit Approximations of Multidimensional Partial Difference Equations," SIAM J. Numerical Anal., 5, 1968, pp. 530-558.
[3.11] D. L. Scharfetter and H. K. Gumme~ "Large-signal Analysis of a Silicon Reed Diode Oscillator," IEEE Trans. on Electron Devices, ED-16, pp. 64-77, Jan 1969.
[3.12] K. Yamaguchi, "Field-Dependent Mobility Model for Two-Dimensional Numerical Analysis of MOSFETs," IEEE Trans on Electron Devices, Vol ED-26, pp. 1068-1074, July 1978.
[3.13] K. Yamaguchi, " A Mobility Model for Carriers in the MOS Inversion Layers," IEEE Trans. on Electron Devices, Vol Ed-30, pp. 658-663, June 1983.
[3.14] S. Y. Oh, P. Vande Voorde, and J. Moll, "An Empirical Mobility Model for Numerical MOSFET Simulation," Hewlett-Packard Semiconductor Technology Conference Proc., pp. 97-104,1984.
[3.15] K. K. Thornber, "Relation of Drift Velocity to Low-Field Mobility and High Field Saturation Velocity," 1. Appl. Phys., Vol. 51, No.4, pp. 2127-2136, April 1980.
[3.16] M. R. Pinto, C. S. Rafferty, R. W. Dutton, " PISCES II: Poisson and Continuity Equation Solver," Stanford Electronics Laboratory, Stanford
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University, California, Sept., 1984.
[3.17] C. H. Price, "Two-Dimensional Numerical Simulation of Semiconductor Devices, " Stanford Electronics Laboratory, Stanford University, California, May, 1982.
Chapter 4
Parasitic Elements Simulation
4.1 Introduction
As we scale down the critical dimensions in integrated circuits, the effect of interconnects becomes as critical as that of devices on the overall circuit performance [4.1),[4.2). The interconnect lines not only act as loads for their drivers but also become a source of noise because the lines are capacitively coupled when they are close to each other. Also, because we scale down the widths of the lines while the lengths of the lines are generally fixed, the resistance of the lines becomes larger. Generally, parasitic inductance is not of concern in on-chip interconnections. However, it is very critical in the packaging of integrated circuits. Careful characterization of these parasitic components in integrated circuits is essential to improve the performance of the circuits.
In this chapter, we discuss simulation programs to extract the parasitic components in integrated circuits. For many of the interconnection geometries where the lines are parallel, two-dimensional simulations give good approximations. However, for geometries like crossing lines and via contact in a multi-level interconnect system, three-dimensional calculations are necessary. To solve the above problems, two-dimensional and three-dimensional simulation programs, SCAP2 and FCAP3, are presented in this chapter. We
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focus on the numerical techniques used in the programs and some basic application examples of the programs. Chapter 15 gives more extensive application examples.
4.2 SCAP2: Two-Dimensional Poisson Equation Solver
SCAP2 is a two-dimensional Poisson equation solving program. For a given set of geometries and bias condition, SCAP2 solves the Poisson equation using the finite difference method with self-adjusting rectangular grid and Incomplete Cholesky Conjugate Gradient (ICCG) method [4.3].
A user can input two-dimensional geometries using the elements shown in Fig. 4.1 which were developed in FCAP2 [4.4] or can build structures using arbitrary polygons. The polygonal input scheme was developed in order to link the two-dimensional process simulator, SAMPLE [4.5], to the FCAP2. (Hence, the name of the program was changed from FCAP2 to SCAP2 (SAMPLE + FCAP2». The user can simulate a problem very easily with these geometrical elements of FCAP2 or the polygonal inputs.
When all the geometries are defined, SCAP2 generates a semi-uniform grid based on the vertices of the geometries. According to the dielectric constants of the insulators and the potential values on the conductors of the problem, SCAP2 sets up a matrix using the five-point difference equation over the grid. The reflective (Neumann) boundary condition is applied on the boundaries of the simulation window. The user can exploit this boundary condition for a symmetric or periodic structure to minimize the size of the simulation window. However, when the geometry of a problem is isolated, the simulation window should be large enough to reduce the effect of the mirror images outside of the simulation window. The matrix is solved by the ICCGmethod which provides a rapid convergence to the solution. From the calculated potential distribution, SCAP2 extracts the amount of charge on each conductor for the given bias condition. The user can obtain the capacitance matrix of a multi-conductor system by applying different sets of biases on the conductors.
One of the good features of SCAP2 is its automatic regrid capability. Since potential varies more rapidly in some areas than others in most of the
Parasitic Elements Simulation |
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Fig. 4.1. Geometry input elements of SCAP2.
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Computer-Aided Design |
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Fig.4.2. Capacitance calculation of a stripline by SCAP2. (a) Geometry of a stripline. (b) Potential distribution on the initial semi-uniform grid. (c) Potential distribution on the automatically adjusted grid.
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problems, it is desirable to have the denser grid in the area of greater potential gradient. Thus, the initial semi-uniform grid is not suitable for the problem. However, since the initial calculation gives the rough potential distribution over the solution area, we can generate a new grid based on the potential distribution. When the regrid command is given after the initial iteration, SCAP2 generates a new grid which conforms with the potential variation. The next iteration on this new grid gives a more accurate solution. By repeating this regrid and iteration, SCAP2 generates the optimal grid for the problem, hence, giving the best solution.
Fig.4.2(a), (b), and (c) show the capacitance calculation of a strip line. The two-fold symmetry allows us to simulate only one quarter of the problem. The geometries and potential contour plot over the initial semi-regular grid are shown in Fig. 4.2(b). A new grid based on the previous potential calculation is shown in Fig. 4.2(c). Note that we have denser grid points under the signal line where the potential gradient is larger than the rest of the area.
The characteristic impedance of the strip line in Fig. 4.2(a) can be easily calculated with SCAP2 for TEM wave propagation with quasi-static approximation. By doing the same calculation as before except for removing the dielectric, we can find the capacitance, Co. The inductance at the high frequency limit, L, can be obtained by
(4.1)
where c is the speed of light in vacuum. The characteristic impedance of the strip line, Zc, is
(4.2)
where C is the capacitance with the dielectric which was calculated previously. The capacitance calculation of polygonal conductors is shown in
Fig. 4.3(a), (b), and (c). There are more grid points between two bean-shaped conductors than the other area on the reallocated grid in Fig.4.3(c). Consequently, the shapes of the inner sides of the conductors are described better than their outer side. This new grid gives a more accurate capacitance value than the initial grid in Fig. 4.3(b) because most of the charges are located at
