dsd11-12 / dsd-12=Проектирование РЧ КМОП ИС / papers / 96_Verification_Techniques_for_Substrate_Coupling

Fig. 20. Measured ramp response of redesigned ADC at 14.4 MHz.

Fig. 21. Measured DNL performance of redesigned ADC.

Using the extracted parasitics in the circuit netlist, several simulations of the ADC were performed to determine the extent of substrate coupling in the design. Fig. 17 shows the results of a simulation which shows the worst-case noise coupling through the substrate as a result of all 12 output buffers switching simultaneously. The nearly 200 mV of substrate injected noise was found to couple to the comparator inputs causing them to trigger falsely. The substrate noise was determined to be mostly a result of the capacitive coupling from the bonding pad, transistor M12, and the ESD device in the output buffer cell, and also from - junction diode (substrate to NMOS drain) turn on due to excessive ground bounce on the DVSS (output ground) line. In the redesign phase, several improvements were made in both the layout and design of the circuit. Some of the key changes made to the layout included routing -wells under the bonding pads and clock lines, reducing the lead inductance of and resistively damping the DVSS and DVDD lines. Design changes were also made to minimize ground bounce on the DVSS line. Since the substrate voltage varies as the second derivative of the switching voltage, kinks in the output voltage create large spikes of noise on the substrate. To prevent this, the output buffer cells were reengineered. The 12 outputs were staggered to prevent simultaneous switching and spaced (in time) to be further away from the sampling clock instant. Fig. 18 shows the simulation results after the redesign efforts. It is apparent that a significant reduction in substrate noise was achieved through the redesign efforts. The ADC was refabricated using the LinEpic1zâ1 (1 m CMOS) process and Fig. 19 shows its die photograph. Figs. 20 and 21 show some test results measured on the redesigned converter. From Fig. 20 it is apparent that there are no missing codes in its ramp response at a sample rate of 14.4 MHz and Fig. 21 confirms that the DNL error is below 0.5 LSB.

1 LinEpic1z is a registered trademark of Texas Instruments, Inc.

VIII. CONCLUSION

This paper discussed advantages and limitations of some commonly employed verification techniques for substrate coupling. A preprocessed boundary element method was introduced in this paper. This method utilizes precomputed parameters to generate an analytical model for substrate impedance in a preprocessing stage. Multipole and local expansions of the generated analytical model are employed to accelerate solution of the boundary element matrix. Results were shown to confirm the accuracy and speed advantages of these techniques. A methodology for the application of these fast techniques to the simulation of substrate coupling in large mixed-signal circuits was presented and verified. An application of the complete methodology to the design of an industrial mixed-signal IC was described. The techniques presented in this paper form a core methodology that can be utilized in a variety of CAD support tools for mixedsignal integrated circuits including circuit verification, circuit optimization for substrate noise problems, and mixed-signal layout synthesis (some work in this area has already been done [7]).

ACKNOWLEDGMENT

The authors thank B. Krenik and M. Chiang of Texas Instruments, Dallas, and T. Schmerbeck of IBM, Rochester, for their support of this project and for several helpful discussions. They are also grateful to R. Rohrer and A. Strojwas of Carnegie Mellon University for their appraisal of this work.

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Nishath K. Verghese (S'91±M'95) received the B.E. (Hons.) degree from Birla Institute of Technology and Science, Pilani, India, in 1990 and the M.S. and Ph.D. degrees from Carnegie Mellon University, Pittsburgh, PA, in 1993 and 1995, respectively.

From 1990 to 1991 he was with the VLSI Design Laboratory at McGill University, Montreal, Canada, where he worked on new circuit implementations of sigma-delta A/D converters and on estimation techniques for power bus current in CMOS logic circuits. At CMU, his research focused on extraction

and simulation techniques for substrate-coupled noise in mixed-signal IC's. In 1994, he worked for five months at the Mixed-Signal Design Department, Texas Instruments, Dallas, applying these techniques to the design of a video A/D converter. He is currently a Senior Member of Technical Staff at Cadence Design Systems, San Jose, CA. His research interests include design and verification of analog and mixed-signal circuits.

David J. Allstot (S'72±M'78±SM'83±F'92), for a photograph and biography, see p. 168 of the February issue of this TRANSACTIONS.

Mark A. Wolfe was born in Pittsburgh, PA, on December 8, 1963. He received the B.S. degree in electrical engineering from Carnegie Mellon University, Pittsburgh, PA, in 1986. He is currently working part-time toward the M.S. degree in electrical engineering at the University of Texas, Dallas.

He joined the Mixed-Signal Design Department of Texas Instruments, Dallas, in 1986 and has worked on hard-disk-drive-related and A/D IC's.