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ALGORITHMIC SERIAL DAC

Pipeline Approach to Implementing a DAC:

where bi = 1 or 0

Approaches:

1.) Pipeline with N cascaded stages.

2.) Algorithmic.

bi z-1VREF vOUT(z) = 1 - 0.5z- 1

Example of an Algorithmic DAC Operation

Realization using iterative techniques:

A

1

2

Assume that the digital word is 11001 in the order of MSB to LSB. The steps in the conversion are:

1.) VOUT(0) is zeroed.

2.) LSB = 1, switch A closed, VOUT(1) = VREF.

3.) Next LSB = 0, switch B closed, VOUT(2) = 0 + 0.5VREF

VOUT(2) = 0.5VREF.

4.) Next LSB = 0, switch B closed, VOUT(3) = 0 + 0.25VREF VOUT(3) = 0.25VREF.

5.) Next LSB = 1, switch A closed, VOUT(4) = VREF + (1/8)VREF VOUT(4) = (9/8)VREF.

6.) Finally, the MSB is 1,

switch A is closed, and VOUT(5) = VREF + (9/16)VREF VOUT(5) = (25/16)VREF

7.) Finally, the MSB+1 is 0 (always last cycle),

switch A is closed, and VOUT(6) = (25/32)VREF

X.6 - CHARACTERIZATION OF ANALOG TO DIGITAL CONVERTERS

General A/D Converter Block Diagram

A/D Converter Types

1.) Serial.

2.) Medium speed.

3.) High speed and high performance.

4.) New converters and techniques.

Sampled Data Aspect of ADC's

t

Tsample = ts + ta

ta = acquisition time ts = settling time

tADC = time for ADC to convert analog input to digital word. Conversion time = ts + ta + tADC.

kT Noise = C

Dual Slope, A/D Converter

Block Diagram:

1

Digital control

Operation:

1.) Initially vint = 0 and vin is sampled and held (Vin* > 0).

2.) Reset by integrating until vint(0) = Vth.

3.) Integrate Vin* for Nref clock cycles to get,

*

4.) The Carry Output on the counter is used to switch the integrator from Vin to -VREF. Integrate until vint is equal to Vth resulting in