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Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of Positive PSRR for the Two-Stage OTA

+

+

VDD

vdd

-

-

 

M3

M4

 

 

 

 

 

M6

M1

M2

 

Cc

-

 

+

vout

M5

 

 

M7

+

 

 

 

VBias

 

 

 

-

 

 

 

 

+

 

 

 

VSS

 

 

 

-

 

 

model-

 

 

+

 

 

 

 

 

 

vdd

 

 

 

-

Must reduce Cc!

 

Vout

 

 

 

Vdd

1.) The M7 current sink causes VGS6 to act like a battery.

2.) Therefore, vdd couples from the source to gate of M6.

3.) The path to the output is through any capacitance from gate to drain of M6.

4.) Resultant circuit

vout

Cc Rout

 

1

 

0dB

RoutCc

ω

 

-60 to

Other sources of

-80dB

PSRR beside Cc

Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA

+

VDD

-

M3

M4

 

 

 

M6

M1

M2

Cc

-

+

vout

M5

 

M7

+

VBias -

? +

vss

-

+

VSS

-

Two mechanisms of vss injection:

M5 or M7 iss

M5

 

+

 

+

VBias

+

VBias -

-

 

vss

+

 

 

-

 

 

vss

 

 

+

 

 

VSS

-

 

 

-

+

 

 

VSS

 

 

 

 

 

 

-

Transconductance injection

Capacitance injection

Allen and Holberg - CMOS Analog Circuit Design

Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA - Continued

Transconductance injection:

Path through the input stage: Not important as long as CMRR is high.

Path through the output stage: vout issRout = gm7vssRout

vout

vss = gm7Rout

Vout

Vss

20 to

40 dB

0dB

1

ω

 

 

 

RoutCout

 

Frequency dependence -

 

1

 

Rout Rout|| sC

 

 

out

Capacitance injection:

 

+

 

vout

vss

Cgd7

Rout

 

-

 

 

 

 

Vout

 

 

 

Vss

 

 

 

 

 

1

 

0dB

 

RoutCgd7

ω

 

 

-60 to

First stage

-80dB

transconductance

 

injection

Reduce Cgd7!

Allen and Holberg - CMOS Analog Circuit Design

Problems with the two-stage OTA:

Insufficient gain

Poor stability for large load capacitance

Poor PSRR

These problems can be addressed using various cascode structures.

We will consider several approaches:

Cascoding the first stage

Cascoding the second stage

Folded cascode

Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode

 

VDD

M3

M4

VDD

V

 

DD

VBP

MC2

 

VDD

VBN

VO1

 

MC3

MC1

+

-

M1

M2

VBIAS

VSS

ro1 (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2

Gain ≈ gm2ro1

Overall gain increased by ≈

gmcrdsc

2

 

 

Requires voltage translation to drive next stage

Requires additional biasing for cascode devices

Common-mode problem at drains of M1 and M2

Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode - Continued

Common-mode improvement:

 

VDD

 

 

M3

M4

 

VDD

V

 

 

DD

 

 

ICM

VBP

 

MC2

 

 

VDD

 

 

VO1

 

MC3

MC1

+

M9

-

 

 

M1

M2

VBIAS

VSS

Common-mode circuitry (M9) maintains Vds of M1 and M2

AV = gm1ro1

ro1 (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2

p1 -1 CLro1

GB ≈ AV|p1| ≈

gm1

CL

 

Output range of this amplifier is poor when used by itself. It needs an output stage to be practical.

Allen and Holberg - CMOS Analog Circuit Design

First Stage Cascode - Continued

Implementation of ICM

 

 

 

VDD

 

 

 

 

 

M3

 

M4

 

 

ICM

 

ICM

 

 

 

 

 

 

 

 

VBP

 

 

V

 

 

 

 

 

DD

 

 

 

 

 

MC2

 

 

 

 

VSS

 

 

 

 

VSS

 

VSS

 

 

 

MC3

 

MC1

 

 

 

 

 

vin

-vin

vin

VSS

VSS

-vin

2

2

2

2

VSS

 

 

M1

 

M2

I5+ICM

VSS

Allen and Holberg - CMOS Analog Circuit Design

Level Translator for First Stage Cascode

VDD

M4

MT2

M6

MC2

MT1

MC1

Vo

VSS

M2

M7

VBIAS

M5

VSS

Allen and Holberg - CMOS Analog Circuit Design

Improved PSRR For Two-Stage OTA

Use cascode to reject Cc feedforward

VDD

 

M3

M4

M6

 

 

 

VB1

M8

 

 

 

M9

Cc

 

 

 

vOUT

-

M1

M2

+

 

M5

 

 

 

VB2

 

M7

VSS

+PSRR is reduced by M9

Disadvantage -

 

 

Miller pole is larger because R1

1

gm9

 

 

positive input common mode range is restricted

Allen and Holberg - CMOS Analog Circuit Design

Complete Two Stage Cascode

 

VDD

M3

M4

 

MT2

VBP

M6

MC2

 

MT1

 

ICM

 

MC1

MC3

Vo

 

VSS

 

M9

M1

M2

VBIAS

M7

 

 

M5

 

VSS

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