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Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-18

CMOS DIFFERENTIAL AMPLIFIERS

Parasitic Capacitances

 

 

 

VDD

 

M3

 

M4

 

 

Cgd4

Cout

 

 

CM

vOUT

vG1

M1

M2

vG2

CT

ISS

VSS

CT = tail capacitor (common mode only)

CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3 COUT = output capacitor ≈ Cbd4 + Cbd2 + Cgd2 + CL

Small Signal Model

 

+

 

+

gm1vgs1

rds3

+

 

C

gd4

 

 

 

 

 

v

 

=

v

=

vgs3

 

 

 

 

 

gs1

 

 

 

 

 

 

 

 

 

gs2

 

 

 

 

 

 

 

r

 

rds4

 

vid/2 -vid/2

 

 

 

 

 

 

ds2

COUT

1

 

CM

g v

 

m2vgs2

 

 

 

 

 

rds1

-

gs3

 

 

 

 

-

 

-

gm3

 

 

m4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

vout

-

We will examine the frequency response of the differential amplifier in more detail later.

Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-19

SLEW RATE

Slew rate is defined as an output voltage rate limit usually caused by the current necessary to charge a capacitance.

dV i.e. i = C dT

For the CMOS differential amplifier shown,

VDD

M3 M4

+

CL - vO

+

M1

M2

vIN

-

ISS

VSS

ISS

Slew rate = CL

where CL is the total capacitance seen from the output node to ground.

If CL = 5pF and ISS = 10 A, then the SR = 2V/ S

Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-20

CMOS DIFFERENTIAL AMPLIFIERS

NOISE

Assumption:

Neglect thermal noise(low frequency) and ignore the thermal noise sources of rd and rs .

Therefore:

i2nd

= KF

 

iDAF

(AF = 0.8 and KF = 10-28)

 

 

fCoxL2

 

 

 

or

 

 

 

 

 

 

vnd2

=

i2nd

=

KF

 

iD(AF-1)

gm2

 

 

2f oCox2WL

 

Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-21

VDD

IDD

veq12

 

2

 

 

veq2

M1

M2

 

 

 

io2

 

 

+

M3

M4

vOUT

veq32

veq42

-

 

VSS

Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-22

CMOS DIFFERENTIAL AMPLIFIERS

NOISE

Total output noise current is found as,

i2

= g

m1

2 v2

+ g

m2

2 v2

+ g

m3

2 v2

+ g

m4

2 v2

od

 

1

 

2

 

3

 

4

Define v2neq as the equivalent input noise voltage of the differential amplifier. Therefore,

i2

= g

m1

2

v2

 

 

 

 

 

 

od

 

 

 

neq

 

 

 

 

 

 

or

 

 

 

 

 

 

g

2

 

 

 

 

v2

= v

2

 

+ v2

 

v2

+ v2

 

eq1

+

m3

 

 

neq

 

 

eq2

gm1

 

eq3

eq4

 

 

 

 

 

 

 

 

 

 

Where gm1 = gm2 and gm3 = gm4

VDD

I DD

v2neq

M1

M2

 

 

 

io2

M3

M4

+

vOUT

 

 

-

VSS

It is desirable to increase the transconductance of M1 and M2 and decrease the transconductance of M3 and M4. (Empirical studies suggest p-channel devices have less noise)

Allen and Holberg - CMOS Analog Circuit Design

Page VI.2-23

CMOS DIFFERENTIAL AMPLIFIERS

Minimization of Noise

v2

= v2

+ v2

g

2

 

v2

+ v2

 

+

m3

 

 

neq

eq1

eq2

gm1

 

eq3

eq4

 

In terms of voltage spectral-noise densities we get,

e2

= e2

+ e2

g

2

 

e2

+ e2

 

+

m3

 

 

eq

n1

n2

gm1

 

n3

n4

 

1/f noise

 

 

 

 

 

 

 

 

 

Let

en2

=

KF

 

=

B

 

 

 

 

 

 

2fCoxWLK'

 

fWL

 

 

assume en12

= en22

and

en32

= en42

 

 

2

 

 

2BP

 

K N 'BN L1 2

 

e

(1/f) =

 

1 +

 

 

 

 

eq

 

fW1L1

KP'BP L3

 

 

 

 

1) Since BN 5BP use PMOS for M1 and M2 with large area.

 

 

 

L1

 

KP'BP

 

 

1

 

 

2

 

2BP

 

2) Make

L3

<

KN'BN

 

12.5

so that

eeq

(1/f)

fW1L1

 

 

 

 

 

 

 

 

 

 

 

Thermal Noise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

W

 

 

 

 

 

 

16KT(1+η

)

 

 

' 3

 

 

 

eeq2

 

 

1 +

 

N L3

 

 

 

 

(th) =

 

 

1

 

 

 

W1

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

3 2KP'I1 L11

 

 

KP' L1

 

 

 

 

1)Large value of gm1. L1

2)L3 < 1.

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-1

VI.3 - CASCODE AMPLIFIERS

VI.3.1-CMOS CASCODE AMPLIFIERS

Objective

Prevent Cgd of the inverter from loading the previous stage. Gives

very high gain.

 

 

 

 

 

 

 

 

 

Cascode Amplifier Circuit

 

 

 

 

 

 

 

 

 

VDD

 

 

 

 

 

VGG2

M3

 

 

 

Miller effect:

 

 

 

 

 

 

vout

Inverter

≈ Gain x C

 

 

 

 

 

 

 

 

 

 

C

in

gd1

 

 

 

 

 

 

 

 

VGG1

M2

 

 

 

Cascode

 

 

 

 

 

 

 

 

 

Cgd1

+

 

 

 

Cin ≈ 3Cgd1

 

 

 

 

 

v1

 

 

v

M1

v

1

 

v

≈ 2

 

in

 

 

 

in

 

 

-

VSS

Large Signal Characteristics

When VGG1 designed properly,

vout(min) = Von1 + Von2

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-2

CASCODE AMPLIFIER-CONTINUED

Small Signal Model

 

 

 

 

 

 

+

 

 

 

gm2v1

gmbs2 v1

 

rds2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rds3

 

vout

 

 

 

+

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vin

v1

 

rds1

 

 

 

 

 

-

gm1vin

 

 

 

-

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(gm2+gmbs2 )v1

 

 

 

 

C1

 

 

rds2

 

 

 

 

+

 

 

+

1

 

 

 

+

 

 

 

 

 

 

 

 

vin

C

rds1

v

gm2 (1+η2)

C3

rds3

v

 

2

 

 

 

 

out

 

gm1vin

 

1

gm2(1+η2)v1

 

 

 

-

 

-

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

Nodal Equations:

(gm1 sC1)vin + (gm2 + gmbs2 + gds1 + gds2 + sC1 + sC2)v1 (gds2)vout = 0

(gds2 + gm2 + gmbs2)v1 + (gds2 + gds3 + sC3)vout = 0

 

 

 

Solving for vout/vin

gives

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s2(C

 

 

 

(sC1-gm1)gm2(1+η)

 

 

 

 

 

 

C +C C )+s (C

+C

2

)(g

ds2

+g

ds3

) +C

3

g

m2

(1+η) +g

ds3

g

m2

(1+η)

3

1 3 2

 

1

 

 

 

 

 

 

 

 

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-3

Small Signal Characteristics

Low-frequency Gains:

vout

 

 

 

 

 

gm1(gds2 + gm2 + gmbs2)

 

 

 

 

 

v

= g

ds1

g

ds2

+ g

ds3

(g

m2

+ g

mbs2

+ g

ds1

+ g

ds2

)

in

 

 

 

 

 

 

 

 

 

 

 

 

gm 1

 

=

2K'(W1/L1)ID1

 

 

 

 

 

 

 

 

 

gds3

 

 

 

λ3ID3

 

 

 

 

 

 

 

 

 

Also (see next page),

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v1

= g

2gm1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v

m2

(1 + η

2

)

 

 

 

 

 

 

 

 

 

 

 

 

in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gain Enhancement:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

 

 

 

 

 

 

 

VGG2

 

 

M3

 

 

 

 

 

 

 

M4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−gm1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vout

 

vout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v

 

g

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in

 

 

 

ds3

VGG1

 

 

M2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2K'W1

 

 

I2

 

 

 

 

 

 

 

 

 

I4

 

 

 

vout

 

 

 

I1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L1

 

 

 

 

 

 

 

I1

 

 

 

 

 

 

 

vin

 

 

 

λI2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vin

 

 

 

 

 

M1

 

 

 

 

 

 

 

But I1 = I2 + I4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

I4 = 24I2 x5 Gain enhancement

Allen and Holberg - CMOS Analog Circuit Design Page VI.3-4

Voltage Gain of M1:

v1 gm1 vin = gm2 ?

What is the small signal resistance looking into the source of M2? Consider the model below:

i 1

gm2vgs2

+

v1= vs2

 

rds3

 

 

 

rds2

 

-

 

 

 

vs2 = (i1 + gm2vgs2)rds2 + i1rds3 = rds2i1 + gm2(vs2)rds2 + i1rds3

or

vs2(1 + gm2rds2) = i1(rds2 + rds3)

Therefore,

R =

vs2

 

 

rds2

+ rds3

rds2 + rd s 3

=

1

 

 

rd s 3

=

 

 

 

 

 

 

 

gm2rds2

 

gm2

1 +

 

 

i1

 

1 + gm2 rd s 2

 

 

 

 

rds2

Some limiting cases:

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

rds3

= 0 R =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

gm2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

rds3

= rds2

R =

 

 

 

 

 

 

 

 

 

 

 

gm2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

rds3

 

 

 

 

 

 

 

 

 

rds3

>> rds2 R =

 

 

 

 

 

 

 

 

 

 

gm2rds2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Therefore, the gain vin to v1 is

 

 

 

 

 

 

 

 

 

v1

gm1(gds2 + gds3)

g

2gm1

 

 

2gm1

v

(g

m2

+ g

mbs2

)g

ds3

m2

+ g

 

 

g

m2

 

in

 

 

 

 

 

 

mbs2

 

 

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