Статьи на перевод PVDF_P(VDF-TrFE) / Controlled Charge Transport by Polymer Blend

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acid SAMs. In contrast, our methods for controlling the charge transport using fluorinated high-k

polymer dielectric blends can be utilized generally, regardless of the dielectric surface and on any other substrate, such as on glass or plastic. We believe that this approach would be a

promising methodology for the development of high-performance complementary metal oxide

semiconductor (CMOS)-based printed organic integrated circuits and can be used to broaden the applications of ambipolar materials in complementary-like circuits.

Conclusions

We have demonstrated high-performance TG/BC OFETs and their complementary electronic

circuits using inkjet-printed conjugated polymers and high-k polymer dielectric blends of

P(VDF-TrFE) and PMMA. The high-k polymer dielectric blends enable the fabrication of wellbalanced CMOS inverters with controlled hole and electron transport and low-voltage operation

due to the high dielectric constant. Both PC12TV12T (p-channel) and P(NDI2OD-T2) (n-

channel) inkjet-printed OFETs showed high µFET values, reaching 0.45 and 0.27 cm2/Vs,

respectively. Importantly, the p-type OFETs characteristics were gradually enhanced in

proportion to the P(VDF-TrFE) concentration in the dielectric blends, while n-type properties

were slightly degraded or not significantly changed. It was explained that the fluorinated dipole

(–C–F bonds) alignment of the P(VDF-TrFE) at the semiconductor-dielectric interface was more

favorable for hole accumulation and transport at the active channel rather than for electron accumulation and transport. Therefore, high, well-balanced electron and hole mobilities and

good VTh values were obtained at a 7:3 blend ratio between P(VDF-TrFE) and PMMA. When

the optimized blended dielectrics were used, high-performance complementary inverters were

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demonstrated with a voltage gain of more than 25, an ideal inverting voltage (Vinv) near ½VDD, a

high noise immunity of ~75% of ½VDD, and low-voltage operation down to 2 V.

Experimental Methods

Field-Effect Transistor and Inverter Fabrication. Corning Eagle 2000 glass substrates were

cleaned sequentially in an ultrasonic bath with deionized water, acetone, and isopropanol for 10 min each. The Au/Ni (15 nm/3 nm thick) patterns used for the S/D electrodes were fabricated

using a conventional lift-off photolithography procedure. The p-type polymer semiconducting

material, PC12TV12T, was synthesized in our laboratory using a previously published

procedure,29 and P(NDI2OD-T2) (ActivInkTM N2200) was supplied by the Polyera Corporation

and used as received. PC12TV12T and P(NDI2OD-T2) were dissolved in anhydrous p-xylene to

obtain an approximately 5 mg/ml solution. The semiconductor inks were inkjet-printed using a piezoelectric-type single nozzle with an orifice 50 [m in diameter (Microfab, Inc.) and a custom-

built inkjet printing machine (UJ 200, Unijet, Inc.) in air. The inkjet-patterned semiconductor

films were thermally annealed at 200 °C for 30 min in a N2-purged glove box. PMMA (Aldrich,

MW = 120 kD) and P(VDF-TrFE) (Solvay, 70:30 molar ratio, random copolymer) were used as

dielectric materials without further purification. PMMA (70 mg/ml) and P(VDF-TrFE) (70 mg/ml) were dissolved in dimethyl sulphoxide (DMSO) and mixed with 5:5, 7:3, and 9:1 blend

ratios. The PMMA and P(VDF-TrFE):PMMA blend dielectric solutions were spin-coated at

~5000 rpm in a N2-purged glove box. After dielectric layer coating, the devices were baked at 80

°C for more than 2 hr in N2 to completely remove residual solvents. The transistors were

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completed by depositing the TG electrodes (Al) via thermal evaporation using a metal shadow

mask.

Thin Film and Device Characterization. The OFET electrical characteristics and the static

characteristics of the complementary inverters were measured using a Keithley 4200-SCS in a N2-filled glove box. The µFET and VTh values were calculated in the saturation region using the

gradual channel approximation equations.30 The C-F characteristics were measured using a built-

in Keithley 4200-SCS CV setup starting from 10 kHz to a 1 MHz frequency. The C-V

characteristics were measured using an Agilent 4284A precision LCR meter and a Keithley

4200-SCS at a frequency of 100 kHz. The surface profiles were measured using a surface profiler (Ambios, XP-1) after inkjet-printing of the P(NDI2OD-T2) and thermal annealing at 200

°C for 30 min, or after spin-coating and thermal baking of the gate dielectric layers. The surface

morphology of the gate dielectric films was investigated via tapping-mode AFM (Nanoscope III, Veeco Instruments, Inc.) at the Korea Basic Science Institute (KBSI).

Acknowledgements

This research was financially supported by a grant (code No. 2011-0031639) from the Center for

Advanced Soft Electronics under the Global Frontier Research Program of the Ministry of Education, Science and Technology, Korea, and a grant from the Basic Science Research

Program through the National Research Foundation of Korea (NRF), funded by the Ministry of

Education, Science and Technology (MEST) (2010-0023180).

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