Статьи на перевод PVDF_P(VDF-TrFE) / Fabrication and Characterization of a MFIS-FET with a PVDF-TrFE

I. INTRODUCTION

Since Kawai discovered strong piezoelectricity in polyvinylidene fluoride (PVDF), PVDF and its copolymer, polyvinylidene fluoride trifluoroethylene (PVDFTrFE), have been intersively studied for a wide range of applications, including nonvolatile memories in organic electronic devices, owing to their ferroelectricity, piezoelectricity, and pyroelectricity, which allow applications, such as electrooptics, electromechanical transducers, and biomedical applications [1,2]. The peculiar properties of PVDF are intimately associated with its crystalline phase (α, β, γ, and δ). The crystalline β-phase PVDF among the four crystalline phases exhibits the strongest ferroelectricity [3]. Copolymerization with trifluoroethylene (PVDF-TrFE) is one way to easily obtain a crystalline β-phase by heat treatment at a temperature between the Curie transition temperature (Tc) and the melting temperature (Tm) [4]. PVDF-TrFE has a large spontaneous polarization of 0.1 C/m2 [5,6], excellent polarization stability, and switching times as short as0.1 microsecond [7]. Further, PVDF-TrFE does not require high-temperature processing, and has an outstanding chemical stability and a low fabrication cost, and is non-toxic.

A ferroelectric-gate field-e ect transistor (Fe-FET), as one of the future nonvolatile memories, has the potential advantage of nondestructive readout, high speed operation, low power consumption, and high density inte-

E-mail: pbe@uos.ac.kr

gration [8,9]. Conventional research on the Fe-FET has focused on utilizing the inorganic ferroelectrics, such as (Bi,La)4Ti3O12 or Pb(Zr,Ti)O3 [10,11]. However, there are some severe problems related with the interfacial reaction like inter-di usion where is due to the high crystallization temperature of ferroelectrics [12]. Recently many attempts to apply organic ferroelectric polymers to ferroelectric memories have been made [13]. For the case of ferroelectric polymers, inter-di usion does not occur because they crystallize at very low temperatures below 200 ◦C as compared with inorganic ferroelectrics.

In this study, we investigated PVDF films as ferroelectric layers for Fe-FETs. Our previous experiments on a metal-ferroelectric-semiconductor (MFS) structure for a Fe-FET using PVDF-TrFE presented the possibility of achieving a low-cost and high-density ferroelectric memory with a low operating voltage [14]. An MFS structure with PVDF showed good ferroelectric properties, but a large leakage current density was a problem to be solved. We think that the leakage problem can be solved by means of selecting a metal-ferroelectric- insulator-semiconductor (MFIS) structure instead of an MFS structure. There are no doubts that very good results have been reported with organic insulators such as poly(styrene-random-methylmethacrylate) copolymer (P(S-r-MMA)) and poly(4-vinylphenol) (PVP) [15,16]. However, in this study, we choose an adequate insulator with good electrical properties. High-k ZrO2 needs a high processing temperature against our initial starting point low process temperature of PVDF-TrFE, ZrO2 is nevertheless, attractive as an insulator for microelec-

tronics and a bu er insulator for the MFIS structure. Now, we try to study the electrical properties and the surface morphologies of a metal-ferroelectric-insulator- semiconductor using PVDF-TrFE and ZrO2. We fabricated MFIS-FETs, and we measured their electrical properties.

II. EXPERIMENTAL

We prepared the ZrO2 thin films and PVDF films on silicon wafers by using a sol-gel wet chemical method. The Sol-gel solution for ZrO2 was synthesized using zirconium propoxide [Zr(OCH(CH3)2)4] and 2-methoxyethanol [CH3OCH2CH2OH]. P-type Si(100) with a resistivity of 1 20 Ωcm was used as a substrate. After cleaning the substrate through a standard process, we spin-coated the ZrO2 solution at 4000 rpm for 25 seconds and then dried it at 400 ◦C for 10 minutes. The dried ZrO2 thin film was finally annealed at 650 ◦C for 30 minutes. The typical film thickness was about 30 nm. Then, the contact holes for the source and the drain regions were opened by using a wet etching method with BOE (bu er oxide etch).

A PVDF-TrFE ferroelectric polymer containing VDF (51 mol%) and TrFE (49 mol%) was used as a ferroelectric material. The PVDF-TrFE copolymer powders were dissolved in the DMF (dimethylformide) solvent. The PVDF-TrFE film was spin-coated on the ZrO2/Si structure. The PVDF-TrFE film was heat-treated at 130 ◦C for 60 min on a hot plate to remove the residual solvents and to improve crystallinity. The typical film thickness was 45 nm. Then, the contact holes for the source and the drain regions were opened by using the dry etching method with reactive ion etching (RIE). Gold electrodes were formed by thermal evaporation. The channel length and width were 10 µm and 60 µm, respectively.

The surface morphologies of both the ZrO2/Si structures and the PVDF-TrFE/ZrO2/Si structures were analyzed using atomic force microscopy (AFM). The capacitance-voltage (C-V) and the current densityvoltage (J-V) characteristics were measured by using HP 4280 and HP 4155C system, respectively. ID-VD (drain current-drain voltage) and ID-VG (drain currentgate voltage) were measured by using a HP 4155C system.

III. RESULTS AND DISCUSSION

In a previous experiment, we fabricated a MFS-FET on a silicon substrate. To reduce the bias voltage, we tried to reduce the thickness of the PVDF-TrFE film. However, when the thickness of the PVDF-TrFE film was decreased, the ID-VG characteristics of the MFIS-FET were not saturated because of the leakage current. Thus,

Fig. 1. (a) C-V characteristics of the Au/ZrO2/Si structure. (b) C-V characteristics of the Au/PVDFTrFE/ZrO2/Si structure. (c) J-V characteristics of the Au/ZrO2/Si and the Au/PVDF-TrFE/ZrO2/Si structures.

the ZrO2 film used a bu er layer to reduce the leakage current and improve the crystallization of PVDF-TrFE films.

Therefore, we investigated the electrical properties of the Au/ZrO2/Si and the Au/PVDF-TrFE/ZrO2/Si structures. Figures 1(a) and (b) show the C-V characteristics of the Au/ZrO2/Si and the Au/PVDFTrFE/ZrO2/Si structures, respectively. The C-V measurements were carried out at 1 MHz. It is worth noting that no ysteresis loops are in Fig. 1(a). The EOT (equivalent oxide thickness) value derived from the accumulation capacitance is 12 nm, and the dielectric constant is

Fig. 2. (a) AFM image of PVDF-TrFE films deposited on silicon. (b) AFM image of PVDF-TrFE films deposited on ZrO2.

calculated to be 11. The small dielectric constant of the film might be explained by the existence of an interfacial SiO2 layer, which was formed during the annealing process in the dry oxygen atmosphere.

In Fig. 1(b), it is found that the C-V plots show hysteresis loops with a clockwise trace as indicated by arrows, which indicates the ferroelectric behavior of the PVDF-TrFE film. It is also shown that the memory window widths gradually increase with increasing applied voltage and saturate at the ±7 V. The memory window width of the Au/PVDF-TrFE/ZrO2/Si measured at a sweep voltage of ±7 V was about 2 V. With increasing sweep voltage, the memory window width becomes larger. Figure 1(c) shows the current density versus applied voltage characteristics for the Au/PVDFTrFE/Si and the Au/PVDF-TrFE/ZrO2/Si structures. The value of the current leakage density of Au/PVDFTrFE/ZrO2/Si structure compared with that of the Au/PVDF-TrFE/Si structure shows that the fabricated ZrO2 film has very excellent insulation.

Figures 2(a) and (b) show the AFM images of PVDFTrFE films fabricated on Si and ZrO2/Si structures. The crystalline lamellas of the PVDF-TrFE films with a

Fig. 3. (a) ID-VG characteristics of the MFIS-FETs. (b) ID-VD characteristics of the MFIS-FETs.

PVDF-TrFE/ZrO2/Si structure are compared with the PVDF-TrFE/Si structure in Fig. 2(b).

Figure 3(a) shows the ID-VG characteristics of the MFIS-FETs. In this measurement, a ysteresis loop was obtained with a counter-clockwise trace, as indicated by arrows. The applied gate voltage sweep range was from -15 V to +15 V, and the drain voltage was fixed at 3 V. The memory window width was about 2.5 V, and on/o ratio was 104.

Figure 3(b) shows the ID-VD characteristics of the MFIS-FETs. The applied gate voltages were from 0 V to +5 V. The drain current was found to be about 0.1 mA when the gate voltage was 5 V. On the other hand, the drain current was as small as 250 nA when the gate voltage was not applied (0 V).

IV. CONCLUSION

We fabricated MIS and MFIS structures and MFISFETs. No hysteretic characteristics were observed in the C-V curve of the Au/ZrO2/Si structure. Hysteresis loops due to ferroelectricity of the PVDF-TrFE film were observed in the C-V curve of the MFIS structure. The memory window width of the Au/PVDF-TrFE/ZrO2/Si structure was about 2 V for the bias sweep range of ±7 V, and the leakage current density value was about 1 ×

10−8A/cm2 at 5 V. Finally, n-channel MFIS-FETs using a PVDF-TrFE/ZrO2/Si structure were fabricated. The ID-VD characteristics had a high drain current of about 0.1 mA at a gate voltage of 5 V. The ID-VG characteristic of the fabricated MFIS-FETs showed hysteresis loops due to the ferroelectric nature of the PVDF-TrFE films with a memory window of about 2 V.

ACKNOWLEDGMENTS

This work was supported by a Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government ministry of Education, Science, and Technology (MEST), (No, R01-207-000-11985-0).

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