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Статьи на перевод PVDF_P(VDF-TrFE) / Control of Thin Ferroelectric Polymer Films

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IEEE Transactions on Dielectrics and Electrical Insulation Vol. 17, No. 4; August 2010

1155

performance. Ferroelectric polymers contain the intrinsic defects arising from imperfect chain configuration, heterogeneous crystalline-amorphous boundaries, graingrain mismatches and residual solvent and these defects usually make it difficult to reduce film thickness drastically for low voltage operation. For FeFET memories with Si channel layers, thermally grown SiO2 interlayers were widely used. In an early work by Yamauchi, SiO2 layers were inserted at both gate/ferroelectric and semiconducting channel/ ferroelectric layer to reduce the gate leakage [98]. A recent work by Salvatore et al. reported a good top gate FeFET device with a P(VDF-TrFE) layer deposited on a thermally grown SiO2 layer. A FeFET with 40 nm thick P(VDF-TrFE) layer was operated at the voltage as low as 6 V with the good data retention capability up to a few days [107]. The high on/off drain current ratio over 105 was almost maintained after 105 endurance cycles programmed in the order of ms time scale.

Thermally curable PVP thin film has been used in a FeFET based on OTFT mainly due to its frequent usage in OTFT as a dielectric layer. We employed a thin PVP layer between vacuum deposited pentacene layer and a β-PVDF one in a FeFET device to provide a smooth interfacial surface on which the pentacene layer had a large crystalline domain with a proper crystal orientation for better hole mobility [115]. We have also confirmed that a PVP layer is effective for a pentacene FeFET with P(VDF-TrFE) in which the PVP layer was spin coated on the gate electrode in a bottom gate transistor structure. An approximately 100 nm thick PVP layer was also inserted between metal gate electrode and a P(VDFTrFE) layer to reduce the gate leakage current in a FeFET with single crystal TIPS-PEN as an active channel [129]. Our device was well operated at the sweeping voltage of ± 30V with good data retention longer than 15 hours. A PVP layer also allowed us to realize a low voltage operation at the voltage less than 15 V in a single crystal TIPS-PEN FeFET in which PVDF/PMMA blend ferroelectric layer was spin coated on the PVP layer to form bilayered gate insulator. Again good data retention longer than 15 hours was obtained in the device [130]. It is obvious that the polarization of all the ferroelectric layers we investigated were not fully saturated at the voltage applied because a significant amount of the voltage was shared with the dielectric PVP layer. Nevertheless, our devices exhibited the good data retention as well as long term stability over 200 days as explained in the previous section. Lim et al have also employed a PVP interlayer in a FeFET with ZnO active channel to obtain low leakage current between gate and drain electrode. More systematic study needs to be done for further understating the phenomena at the interface of the bilayer [127].

We have recently developed a new polymeric gate dielectric interlayer of a cross-linkable poly(styrene- random-methylmethacrylate) (P(S-r-MMA)) copolymer with a good thermal and chemical resistance in bottom gate

FeFET memory with pentacene active layer and P(VDFTrFE) one [153]. We chose the copolymer interlayer with the following reasons. First of all, good miscibility of PMMA with P(VDF-TrFE) insured the solid and firm interface with surface energy matched with each other. Secondly, a cross-linkable polymer was required because a polymeric interlayer should be chemically and thermally resistive to remain stable upon the spin coating and subsequent thermal annealing of a thin P(VDF-TrFE) layer. A thin uniform P(VDF-TrFE) film was successfully formed with well defined ferroelectric microdmains on an interlayer. Thickness of the interlayer turned out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. We carefully controlled the film thickness ranging from 5 to 30 nm with the film roughness maintained. An interlayer inserted between gate electrode and P(VDF-TrFE) layer significantly reduces gate leakage current, leading to source-drain OFF current of approximately 10-11A in particular when its thickness becomes greater than approximately 25 nm as shown in Figure 16. A reliable FeFET device shows a clockwise I-V hysteresis with drain

current bistablility of 103 at ±40 V gate voltage. The types

and properties of interlayers employed in ferroelectric polymer memory elements are described in Table 4.

Figure 16. (a) Transfer characteristic curves (IDS-VG) at VD= -5 V of pentacene FeFETs with 6 different P(S-r-MMA) interlayers. (b) Plots of ON and OFF current as a function of the P(S-r-MMA) interlayer thickness. While ON current remains all similar, OFF current gradually decreases with the interlayer film thickness up to approximately 25 nm [153].

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Table 4. Characteristics of ferroelectric memory devices with various inter layers.

Inter

Device

Thickness

 

 

 

 

 

of PVDF-

Major role of Interlayer

Device characteristics

Refs

layers

structure

TrFE (nm)

 

 

 

 

 

 

 

 

 

 

 

 

Inorganic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SiO2

MFIS

36~450

Reduce leakage current

Operation voltage: ±15V at 1KHz

Operation voltage:±3V

[100]

 

 

 

 

Threshold voltage shift: 2.8V

 

Nonferroelectric layer

[102]

 

 

 

 

Flatband voltage shift at –10 to +6 V

formation

[103]

Ta2O5

MFIS

100

Reduce leakage current

Operation voltage: ±4V

 

 

[77]

 

 

 

Prevent the shift of C-V curve

Memory window of 2.9V

 

 

 

HfTaO

MFIS

46

Reduce leakage current

Operation voltage: ±3V

 

 

[105]

 

 

(blended

Prevent the shift of C-V curve

Memory window width: 1.2V

 

 

 

 

 

with PMMA)

Increase retention property

Data retention: 4hr

 

 

 

 

 

 

 

 

 

 

 

Organic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PEDOT

MFIM

65~210

Low voltage operation

Operation voltage ±5.2V

 

 

[75]

:PSS

 

 

Reduction of switching time

Switching time : 103 times faster at 100Hz and 80MV/m than Al

 

 

 

 

 

electrode

 

 

 

 

 

 

 

 

 

 

 

Ppy-

MFIM

50

Increase of the crystallinity

Coercive voltage: 2.6 V

 

 

[125]

PSSH

 

 

Enhance the crystal dipole orientation

Switching time: 30 μs

 

 

 

 

 

 

 

Fatigue: more than 1x107 cycles

 

 

PEDOT

MFIM

50

Low voltage operation

Coercive voltage: 2.6V

 

 

[151]

-PSSH

 

 

Enhanced fatigue property

1x107 of switching cycles

 

 

 

SAMs

MFIM

30~250

Preferred crystal orientation of a axis

Operation voltage: ±20V

 

 

[140]

 

 

 

perpendicular to CH3-terminated SAMs

Coercive voltage: 11.2V

 

 

 

PTFE

MFIM

40

Epitaxy with PVDF-TrFE crystals

1.7μC/cm2 at ±30V operation

 

 

[148]

 

 

 

-(010)PVDF-TrFE //(100)PTFE

Fatigue cycles of 5x108 with 104Hz at ±20V

 

 

 

 

Enhanced thermal hysteric behavior

 

 

 

 

 

 

 

 

 

 

 

PVP

MFIS

100

Prevent the shift of C-V curve

Operation voltage: ±30V

Retention: 40hr (25% reduction of

[152]

 

 

 

 

Con/Coff ratio: 3.82

bistability)

 

 

FeFET

200~400

Reduce gate leakage current

ZnO active layer

TIPS-PEN active layer

[127]

 

 

 

 

-operation voltage: ±40V

- operation voltage: ±40V

[129]

 

 

 

 

-Ion/Ioff ratio: 104

- Ion/Ioff ratio: 5x103

 

 

 

 

 

-gate leakage current 10-10A

- retention property: 5x104 sec

 

 

 

 

 

 

- environmental stability >40days

 

PVA

MFIS

200

Prevent the shift of C-V curve

Operation voltage: ±30V

Con/Coff ratio: 4.076

[152]

P(S-

FeFET

350

Reduce gate leakage current

Operation voltage: ±40V

 

 

[153]

rMMA)

 

 

 

Enhanced Ion/Ioff ratio 102 times with over 25nm P(S-r-MMA)

 

3.4 PATTERNING OF FERROELECTRIC

POLYMERS

Micro/nanofabrication processes for ferroelectric polymers have been established not only for potentially realizing high density memory devices but also for understanding the structure-ferroelectric properties relation in the confined geometry. A direct pattern transfer technique was developed to form microstructures in the polymer film by photoetching using X-rays [154]. Upon increasing exposure to X-ray beam generated by synchrotron radiation source, a semimetallic photodegrated product was produced in P(VDF-TrFE) film prepared by LB method. The method was easily employed for micropatterning the ferroelectric film when combined with a nickel wire mesh mask, leading to regular arrays of ferroelectric domains of 16 μm in size. The same group also utilized X-ray source to fabricate micropatterned ferroelectric PVDF polymer vacuum-deposited on a Si substrate [155]. They also found the substantial chemical

modification of the PVDF film by the enhanced conjugation in the degraded polymer chains due to the loss of fluorine atoms. Alternating α and β type patterns were fabricated by laser ablation of a P(VDF-TrFE) film in which the irradiated region of an initial β P(VDF-TrFE) film was transformed into α due to thermally induced conformation change of the polymer [156].

Many attempts have been made to produce micropatterns by non-conventional soft lithographic techniques. Recently Hu et al have fabricated nanometer scale patterns of PVDF using nano-imprinting lithography [157]. The confined crystallization and resulting molecular ordering of α type PVDF crystals was successfully demonstrated in the nanoscopic trenches produced by nano-imprinting. The ordering of the PVDF crystals was attributed to the suppression of heterogeneous nucleation by the confinement as well as by partial chain alignment due to flow during the imprinting. Further understanding of the crystallization of PVDF in the confined geometry was made by Steinhart et al.

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in which the confined crystallization of PVDF occurred inside nanopores of an anodized Al oxide membrane [158,159]. They revealed the 2D confinement again suppressed branching as well as spherulite formation and selected specific crystal orientation during growth. We utilized capillary molding technique and reported micron scale pattern formation of PVDF with controlled crystal orientation similar to ones of a PVDF confined in the 1D lines reported previously [160]. The previous works including ours, however, do not provide a practical patterning technique that produces isolated polar ferroelectric micro or nanodomains of PVDF because (1) the crystalline structure dealt with was nonpolar α type and (2) some polymer remained on the imprinted regions, resulting in non-isolated patterned domains.

We have recently demonstrated a micro-patterning technique that produces patterned arrays of isolated ferroelectric γ type domains embedded into non-polar α structure in thin PVDF films [139]. The method is based on using micro-imprinting of a spin cast α type PVDF film. The localized regions pressed by a patterned PDMS mold turn into polar γ type structure under certain temperature and pressure. We also reported that a capacitor fabricated with the pressed PVDF thin film showed reasonably high remanent polarization of approximately 6 μC/cm2, with the coercive voltage of approximately 11 V. The localized polar ferroelectric domains are successfully scaled down to a few hundred nanometers as shown in Figure 17.

(a)

500 nm

(b)

200 nm

Figure 17. (a) A SEM image of PVDF pattern with 2 μm circular holes fabricated by microimprinting process. The pressed regions look flat with ferroelectric γ crystals, while highly stretched α crystalline lamellae were seen in the un-pressed, elevated ones. The inset shows a schematic of the patterned arrays of ferroelectric γ crystals surrounded by the elevated non-polar α crystalline domains. (b) The elastomer with circular posts of 400 nm in diameter produced the isolated and indented ferroelectric PVDF pattern arrays as demonstrated with an AFM image [139].

We have also developed a method to fabricating ferroelectric alternating α and β-type PVDF line patterns on Au substrate based on micro-contact printing [115]. The substrate selective α and β crystal formation of PVDF film on Au substrate allowed us to fabricate micropatterned β crystals when a PVDF thin film was spin coated and subsequently annealed on a chemically patterned Au substrate with SAMs. A 250 nm thick PVDF film prepared on a microcontact printed Au substrate with COOH-terminated SAMs apparently displays a micropattern in which α type crystals were dominantly formed on COOH-treated regions while β crystals were on the bare Au regions.

Microimprinting was employed to fabricate patterned arrays of a ferroelectric P(VDF-TrFE) film. Zhang et al presented the optimal microimprinting conditions of P(VDF-TrFE) thin films for high remanent polarization and high poling-induced surface potential [161]. Nanometer scale ferroelectric domains were fabricated of a P(VDFTrFE) film from LB method after annealing in the paraelectric phase. M. Bai et al have confirmed that the nanodomains retain the ferroelectric properties of the bulk material and thus be suitable for use in high density nonvolatile memory [162]. Recent work by Hu et al. has suggested that nanopatterned ferroelectric polymer domains were potentially useful not only for fabricating high integration density of cells larger than 33 Gbit/in2 but also for significantly reducing a coercive field to approximately 10 MV/m, well below previously reported bulk values [163]. Nano-imprinting technique allowed the preferential crystal orientation with very low level of structural defects in the patterned domains, leading to more uniform switching behavior from cell to cell as schematically depicted in Figure 18a.

Figure 18. (a) Schematic diagram of fabrication of high-density arrays of a P(VDF-TrFE) film by nanoimprinting process. (b) PFM piezo response phase of an array of P(VDF-TrFE) nanostructure fabricated by nanoimprinting [163].

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Table 5. Critical design rules of materials and process components for ferroelectric polymer memory.

Components

Properties

Design rules

Issues to be considered

 

 

 

 

 

Degree of crystallinity

as high as possible for high remanent

~90% for PVDF-TrFE

 

polarization

~50% for PVDF

 

 

 

Orientation of crystals

b axis aligned parallel to the electrode normal

The orientation of ac plane on the electrode should

 

be optimized.

 

 

 

Ferroelectric polymers

Size of crystal domains

as large as possible for good fatigue

Film roughness should be minimized

 

 

Film thickness

as thin as possible for low voltage operation

Degree of crystallinity decreases with decrease of

 

film thickness.

 

 

 

 

Dielectric constant

as high as possible for low voltage operation

~10 for both PVDF-TrFE and PVDF

 

 

Nanocomposites with high k materials

 

 

 

 

Dielectric constant

as high as possible for low voltage operation

High electric breakdown field is required

Interlayers

Film thickness

as thick as possible for low leakage current

Optimization is needed.

 

 

as thin as possible for low voltage operation

 

 

 

 

Conductivity

as high as possible for low voltage operation

Only a few Polymer conductors are suitable.

 

and good fatigue

 

 

 

Semiconductors

Field effect mobility

as high as possible for high speed operation

Less than the order of 1 cm2/Vs for most of organic

and polymer semiconductors

 

 

 

 

 

 

 

Electrodes

Source/drain

work function matching with semiconductor

Au is suitable for most of organic semiconductors

Gate

noble metals for high switching and good

Depolarizing layer by the reaction with ferroelectric

 

 

fatigue

polymers should not be formed.

 

 

Patterns

Patterned domains

as small as possible for high density memory

Scalability

Material damage during patterning process should

 

 

 

be minimized.

Direct writing by surface probe microscope is known as an efficient way to fabricate a nanometer scale pattern surface of PVDF and P(VDF-TrFE) [69,70,164-166]. In particular piezoresponse force microscope (PFM) has been used to manipulate and image polarization of ferroelectric polymer films prepared by either LB method or spin coating and thus to achieve the polarization control with a resolution below 50 nm. For example, a P(VDF-TrFE) film by LB method exhibited a local hysteresis loop with the coercive voltage of approximately 10 V corresponding to macroscopic switching field of approximately 150 MV/m at 10 nm depth below the tip. This nanolithographic method is potential for high-density data storage and retrieval at densities exceeding 250 Gbit/in2. Furthermore, combined with polarization domain patterning, the domain-specific photoreduction reaction, which occurred in a metal ion solution under ultraviolet irradiation, enabled deposition of nanoparticles in complex configurations on the ferroelectric PVDF surface [166]. PFM was successfully employed to visualize the polarization switching of a nanopatterned P(VDF-TrFE) film fabricated by nanoimprinting, allowing the individually addressable patterned arrays as shown in Figure 18b [163].

Lateral modulation friction force microscope (LM-FFM) has been also useful not only for controlling the molecular orientation of P(VDF-TrFE) crystals but also potentially for

nanopatterning the thin films [142, 167]. Localized friction by a surface probe tip at high temperature induced the reorganization of polymer chains along the scanning direction, giving rise to well ordered ferroelectric crystalline edge-on lamellae aligned perpendicular to the tip-scan direction.

4 SUMMARY AND OUTLOOK

In this review article, we mainly focused on various material and process issues of thin ferroelectric polymers for nonvolatile ferroelectric polymer memory. In particular most of the article was devoted to describe the state of art in the development of memory devices based on PVDF and P(VDFTrFE). Followed by the overview of ferroelectric memory architectures, basic characteristics of ferroelectric polymers and various methods for sub micron film fabrication, the recent development of three main memory elements were in details elaborated such as MFM, MFIS, and FeFET with main emphasis on various memory functions including operating voltage, memory margin, fatigue, imprint, thermal budget and retention. In the last part, we discussed the challenging material and process issues for full realization of polymer ferroelectric memory which included (1) the control of polymorphic crystals, crystallization and crystal orientation,

(2) the control of interfaces of ferroelectric polymers with

IEEE Transactions on Dielectrics and Electrical Insulation Vol. 17, No. 4; August 2010

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metal and semiconductor and (3) the fabrication of patterned ferroelectric arrays. We comprehensively summarized the critical design rules for high performance non-volatile ferroelectric polymer memory in Table 5. It is commonly accepted that the device performance of ferroelectric polymer memories are yet to be critically compared with the leading edge memory devices based on inorganic materials. Further effort to establish the clear relationship between ferroelectric polymers and memory properties will be obviously required to advance the polymer memory technology in materials design, preparation, device fabrication and characterization. Nonvolatile memory based on ferroelectric polymers is, however, still promising by virtue of low cost, device flexibility, high performance and environmental compatibility. These unique characteristics make the ferroelectric memories attractive as an alternative or supplementary technology to the current memory technology. Among many other candidate organic and polymer memories based on the mechanisms such as resistive, charge trapping and transfer, and ionic conduction, ferroelectric polymer memory will in particular play a major role in the initial stage of development of this filed and thus find its way for the emerging applications in organic electronics combined with printing technology near future.

ACKNOWLEDGMENT

This work was supported by “SYSTEM2010” project and the 0.1 Terabit Non-volatile Memory Development funded by the Ministry of Commerce, Industry and Energy of the Korean Government, the Korea Science and Engineering Foundation(KOSEF) grant funded by the Korea government(MOST)(No. R11-2007-050-03001-0). We are also thankful for financial support from Samsung Electronics, Co., Ltd.

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Cheolmin Park is an Associate Professor of the Department of Materials Science and Engineering at Yonsei University. He was born in Pusan, Republic of Korea, in 1970. He received the B.S. degree in textile engineering in 1992 and the M.S. degree in polymer and fiber science in 1995 from the Seoul National University. He received the Ph.D. degree in materials science and engineering

from Massachusetts Institute of Technology (with E.L. Thomas) in 2001. From 2001 and 2002, he was a post-doctoral fellow in chemistry and chemical biology of Harvard University. He joined the Department of Metallurgical System Engineering of Yonsei University in 2002. His research interests include polymer physics, self assembled block copolymers, ferroelectric materials, microand nanofabrication, and polymeric opto-electronic devices such as memories and transistors.

Youn Jung Park was born in Taegu, South Korea and received the B.S. and M.S. degrees in metallurgical engineering from Yonsei University, Seoul, Korea. She is currently pursuing the Ph.D. degree in materials science and engineering in Yonsei University. She is presently involved with ongoing research on control of semicrystalline polymer structure in ferroelectric thin film for the nonvolatile memory applications, under the guidance of Prof. Cheolmin Park.

Insung Bae was born in Suwon, South Korea and received the B.S. degree in metallurgical system engineering from Yonsei University, South Korea in 2008. He is currently pursuing the M.S. degree in material science and engineering in Yonsei University with Prof. Cheolmin Park. His current research interests have been concentrated on the ferroelectric polymers, semiconductor/dielectric interface control

for high performance memory applications.

Seok Ju Kang received the B.S. degree in metallurigical engineering in 2005 and currently pursuing the Ph.D. degree in material science and engineering at Yonsei University with Prof. Cheolmin Park, Seoul, Korea. His current research interests are centered on the control of polymer crystal, ferroelectric thin film transistor and crystal nanoconfinement of PVDF and P(VDF-TrFE) materials.

Jiyoun Chang was born in Incheon, South Korea and received the B.S. degree in metallurgical engineering from Yonsei University, Seoul, Korea in 2007. She is currently working on the M.S. degree in materials science and engineering in the same institution and has joined Nanopolymer Laboratory. Recently, under Prof. Cheolmin Park’s guidance, she researches on controlling orientation of molecular and microstructure

of crystalline polymer, especially ferroelectric polymer as well as its application as ferroelectric field effect transistor (FeFET).