Статьи на перевод PVDF_P(VDF-TrFE) / Control of Thin Ferroelectric Polymer Films

2.2 METAL/FERROELECTRIC

POLYMER/INSULATOR/

SEMICONDUCTOR (MFIS) DIODES

A potential nonvolatile bistable capacitor memory element of a metal/insulator/semiconductor architecture was proposed by Yamauchi et al. [98,99] in which a ferroelectric P(VDFTrFE) thin film was sandwiched between two SiO2 insulator films to prevent carrier injection into the ferroelectric thin film. The basic characteristic capacitance hysteresis was observed by the ferroelectric polarization reversal when the device was operated with ±60V at 1 MHz. A metal/P(VDF- TrFE)/silicon-oxide/n-type silicon semiconductor has been demonstrated, combined with Langmuir-Blodgett film process for deposition of highly ordered P(VDF-TrFE) thin film. A clear capacitance hysteresis was observed as the gate voltage

was cycled between ±25 V with a capacitance dynamic range

of 8:1 [100]. The MFIS device also exhibits the threshold voltage shift of 2.8V on SiO2 insulator ineffective for nonvolatile memory application at zero gate voltage. The same group also reported a similar MFIS device with much thinner P(VDF-TrFE) film of approximately 35 nm in which the capacitance hysteresis exhibited a zero-bias on/off capacitance ration of over 3:1 and a symmetric memory window 1 V wide at the operating voltage of ±3V [101]. The device, however,

showed a poor data retention of approximately 15 min at room temperature, possibly due to either the leakage or polarization instability in the unsaturated film.

More extensive and detailed study was performed by Lim et al of the electrical properties of MFIS using SiO2 insulator and P(VDF-TrFE). They have observed that the (C–V) hysteresis and bidirectional flatband voltage shift at −10 to +6 V, depending on the polarization field direction and remnant polarization at the ferroelectric PVDF copolymer gate, presents a memory window [102]. In particular, the observed asymmetry of the negative flatband-voltage shifts in the negatively poled ferroelectric polymer state results from the depletion layer formation, which reduces the field across the polymeric gate. Internal field due to negative and positive bound charges within PVDF copolymer and SiO2, respectively, influences polarization switching by pinning of dipoles. The recent work by Henkel et al. has systematically examined the electrical properties of MFIS devices with SiO2 insulators as a function of the thickness of P(VDF-TrFE) layers [103]. They observed that a thin non-ferroelectric interlayer was formed between Al electrode and a P(VDFTrFE) layer which was responsible for the reduced polarization as the P(VDF-TrFE) layer became thinner. Long time measurement revealed imprint and fatigue-like behavior in their devices.

Fujisaki et al [77] have recently demonstrated that the intrinsic negative flatband-voltage shift on SiO2 insulator observed in the previous works is largely eliminated by employing an interlayer of a 3 nm thick Ta2O5 as shown in Figure 9. Rectangular-shaped capacitance-voltage hysteresis loops were obtained with a voltage sweep range narrower than 5 V. The maximum memory width was 4.7 V [77]. The authors have also improved the data retention of MFIS devices with 100 nm thick P(VDF-TrFE) layer by adding a small amount of poly(methyl methacrylate) (PMMA) in the ferroelectric layer with the proper control of the crystallization of the blended ferroelectric layer [104]. A MFIS with Ta2O5 insulating layer showed a good data retention longer than 106 seconds when measured at 0 V after the programming with ±5 V for 1 s. A continuous work by Lu et al. has also demonstrated that MFIS diodes with P(VDF-TrFE) and PMMA blend ferroelectric layer exhibited a wide memory window of 1.2 V for the voltage sweep of ±3 V when 6 nm thick HfTaO interlayer was inserted [105].

Figure 9. Capacitance-voltage hysteresis curves of a Au/100 nm P(VDFTrFE)/3 nm Ta2O5 /Si MFIS diode. The arrows denote the clockwise rotations of the hysteresis loops [77].

Furukawa et al have recently reported the switching characteristics of an Au/P(VDF-TrFE)/n-Si MFS diode by simultaneous measurement of charge and capacitance changes induced by a double frequency voltage. Interestingly polarization reversal toward the negative side was impeded by depletion layer formation at its early stage but was eventually completed via a constant current process. The authors concluded that the switching dynamics under a negative voltage was controlled by the rate of minority carrier generation in the depletion layer [106].

Ferroelectric polymer MFIS memory units with organic semiconductors are also of great interest for potential realization of organic field effect transistor memory. A MFS device with a p-type pentacene active layer vacuum-deposited exhibited the gate voltagecapacitance hysteresis similar to that with p-type Si active layer. In order to improve the interfacial properties between a ferroelectric layer and either organic semi-conductor or metal electrode, an insulating

polymer layer has been employed. In the case of MFIS device architecture, an interlayer provided a homogeneous and flat surface on which pentacene molecules are effectively deposited to form the crystal domains much larger and more homogeneous than ones without the interlayer. On the other hand, an interlayer between gate electrode and P(VDF-TrFE) layer in MIFS turned out very effective to prevent a possible leakage current through gate electrode. We will discuss the issue of interlayers either in MFIS or in FeFET devices later in details.

2.3FEFETS

2.3.1SI BASED FEFETS

Ferroelectric polymer memory devices based on the drain current modulation in a type of field effect transistor (FET) architecture have been widely investigated due to their nondestructive readout capability and a smaller cell size. The success in developing the ferroelectric memory units of MFIS structure made it much easy to realize a ferroelectric FET (FeFET). With a 1 μm thick ferroelectric P(VDF-TrFE) layer as a gate insulator, a FeFET was successfully fabricated, based on the modified CMOS process in order to avoid high temperature processes before deposition of the ferroelectric polymer layer. The device with the channel length and width of 2 and 12 μm, respectively exhibited an excellent on and off current bistability greater than 106 order but with the high programming voltage over 200 V [98]. Great improvement of both operating voltage and long time reliability has been made in a silicon MOSFET device with sub 100 nm thick P(VDFTrFE) gate insulating layer. Both channel length and width are varied from 2 to 50 μm [107]. In particular, a FeFET with 40 nm thick P(VDF-TrFE) layer showed a saturated drain current-gate voltage hysteresis curve at the operating voltage as low as 6 V with the good data retention capability up to a few days. The high on/off drain current ratio over 105 was almost maintained after 105 endurance cycles programmed in the order of ms time scale.

2.3.2 PENTACENE BASED FEFETS

Due to the great suitability of organic field-effect transistors (OTFTs) for low-cost, low-performance logic circuit applications on flexible substrates, OTFTs with ferroelectric polymer films, i.e. FeFETs with organic active layers have been demonstrated potentially for all organic non-volatile memory, at the beginning of the research invariably with the use of evaporated pentacene as the semiconductor material. Schroeder et al utilized nylon poly(m-xylylene adipamide) (MXD6) as a ferroelectric gate dielectric in a pentacene FeFET and demonstrated an on/off ratio of 200 at 2.5 V gate bias, 30 at zero gate bias and a retention time of three hours [108]. The programming time, estimated from the reported ferroelectric switching current duration, exceeds 200 ms. Unlike the most of ferroelectric polymers including PVDF and P(VDF-TrFE), MXD6 exhibits ferroelectric properties in its amorphous state which may be potentially beneficial for scalibility of memory unit cells.

Unni et al also obtained a similar on/off ratio and retention time from a pentacene FeFET based on P(VDF-TrFE). In spite of the interesting memory properties observed, both reports do not successfully prove that the memory functionality is driven by ferroelectricity and not by a secondary effect such as charge trapping [109]. The current modulation by ferroelectricity would have been demonstrated by, for example, a sudden rise in the drain current when the gate field reached the coercive field of the ferroelectric insulator layer. In fact the gate field applied in the transfer curve measurement by Unni et al is much lower than the coercive field of their ferroelectric material. Matsuo et al have reported the expected drain current increase at around the coercive voltage and a data retention time of a week, but the onand off-states after this time differ only by a factor of 0.5 [110].

The more comprehensive understanding of a pentacene FeFET with a P(VDF-TrFE) thin film was made by Nguyen et al. in which they observed that the large positive shift of the transfer characteristic up to 25 V was attributed to the accumulation of mobile charge carriers in pentacene layer even during the device OFF state [111]. The detailed experiments revealed that negative polarizationcompensating charges injected to the insulator region next to the pentacene layer mainly contributed to the positive shift of the transfer curve. The same group also reported the enhanced memory performance in a pentacene FeFET containing a strained P(VDF-TrFE) film [112]. Uniaxial stretching of approximately 1 μm thick P(VDF-TrFE) film attached to a flexible metalized PET substrate improved surface morphology and polarization properties of the ferroelectric polymer at lower processing temperatures. In spite of the 200 % enhancement in field effect mobility of the pentacene layer arising from the reduced surface roughness, the resultant memory performance turned out isotropic and yielded slightly improved current amplitude and on/off ratio.

A low voltage operation of a pentacene FeFET with a P(VDF-TrFE) film was accomplished by the employment of a thin P(VDF-TrFE) gate insulator prepared by LangmuirSchaefer technique. Nguyen et al [113] have demonstrated a pentacene FeFET with 10 monolayered P(VDF-TrFE) film exhibiting on/off ratio of 103 at the operating voltage of ±15V. The authors, however, mentioned that mobile charge trapping at the ferroelectric-semiconductor interface worsened the current retention in particular when the substrate was plasmatreated for LB film coverage. Further improvement of a pentacene FeFET has been made by Lee et al who cured a P(VDF-TrFE) film at 160 °C and subsequently quenched it to room temperature by blowing N2 gas [114]. A FeFET with the resulting ferroelectric film was fabricated on a flexible polyethersulfone substrate. The device operated under the low voltage write-erase pulses of ±13 - 20 V with field effect mobility of 0.1-0.8 cm2/Vs. The retention time was over 104 s with the short switching pulse of 50 ms.

We have also recently described a method to fabricating a FeFET based on ferroelectric β-type PVDF thin films on Au substrate by the humidity controlled spin casting combined with rapid thermal treatment [115]. Our device with the β- PVDF thin film has much higher thermal stability up to 160

°C than P(VDF-TrFE) due to the higher Curie temperature of the PVDF film. A FeFET fabricated also shows a drain

current bistablility of 100 at zero gate voltage with ±20 V gate voltage sweep.

Special caution should be made when one designs a non-volatile memory based on OTFT since polymer electrets with transient electric charges frequently give rise to a saturated drain current hysteresis similar to one observed with a ferroelectric polymer layer. For instance, poly(vinyl alcohol) (PVA) insulating layer not only influences the morphology of the active semiconductor but also the distribution of the localized states at the semiconductor-dielectric interface which gives rise to an inherent hysteresis temperature-dependent due to charge trapping at the interface [116-118]. In addition, another polymer electrets, poly(α-methylstyrene) (PαMS) has also shown nonvolatile memory effect in a pentacene OTFT device because of its charge trapping capability like flash memory [119]. Although the intrinsic slow discharging rate of the trapped charges gives rise to OTFT memories with fairly good data retention greater than 100 h and thus in some senses are very attractive for nonvolatile polymer memory applications in the polymer electrets, the trapping-detrapping process is not thermodynamically driven but meta-stable and should be strictly distinguished from ferroelectric mechanism [120]

2.3.3 POLYMER SEMICONDUCTOR BASED

FEFETS

High-performance solution-processed polymer FeFETs have been demonstrated by Naber et al consisting of a P(VDF/TrFE) ferroelectric copolymer as gate insulator and poly[2-methoxy, 5-(2'-ethyl-hexyloxy)-p-phenylene-vinylene] (MEH-PPV) as a semiconductor [121]. The polymer FeFETs have a remanent on/off ratio of several orders of magnitude at zero gate bias, a long data retention time of the order of 104 minutes, a high programming cycle endurance of more than 1000 and a short programming time of 0.3 ms as shown in Figure 10. The high on/off ratio mainly originates from the large on-current in the semiconducting channel which is indicative of a large surface charge density ρ of 18 mC/m2 which is one quarter of the remanent polarization of the ferroelectric. A semiconducting blend layer of MEH-PPV and the fullerene derivative [6,6]-phenyl–C61–butyric acid methyl ester (PCBM) consisting of polymer based interpenetrating network allowed ambipolar charge transport in an OTFT. When a P(VDF-TrFE) layer was employed as a gate dielectric layer in the OTFT, a FeFET device exhibited the polarity channel remanently switched from p-type to n- type and back, depending on the polarization state of the ferroelectric layer [122].

A FeFET with both high field effect mobility and high charge density has been demonstrated with regioregular poly(3-hexylthiophene) (rr-P3HT) and P(VDF-TrFE), respectively. High field effect mobility of approximately 0.1 cm2/Vs was achieved in rr-P3HT active layer with a top-gate layout which significantly reduced interfacial roughness between semiconductor and ferroelectric thin film [123]. Low voltage operation of a FeFET is one of the most critical factors

for non-volatile memory applications. Most of FeFETs based on OTFTs required relatively high operating gate voltage sweep over ±60 V. The low programming voltage can be obtained by (1) ferroelectric polymer film as thin as possible and (2) insulating layer with high dielectric constant. The reduction of film thickness of P(VDF-TrFE) less than 100 nm often causes many structural defects in the film giving rise to gate leakage in the device operation.

Figure 10. Drain current hysteresis as a function of gate voltage in a FeFETs containing a 1.7 μm thick P(VDF-TrFE) layer. The arrows show the clockwise hysteresis of the drain current consistent with accumulation and depletion of p- type charge carriers [121].

The same group has resolved this problem by using cyclohexanone as a solvent for P(VDF-TrFE) to give thin, smooth and defect-free ferroelectric films [74]. An organic FeFET memory fabricated with thin solution processed P(VDF-TrFE) gate dielectric has programming voltage of 15 V with 3 hour retention capabilities [74]. Extrapolation predicts data retention exceeding 10 years. In order to enhance the dielectric constant of a ferroelectric polymer layer, a solution processed composite film of P(VDF-TrFE) and barium titanate (BT) has been also utilized as a gate dielectric layer in an organic FeFET with rr-P3HT semiconductor. Yildirim et al. argued that the composite films exhibited high specific volume resistivities combined with dielectric constants of up to 51.5 at 1 kHz and the FeFET fabricated operated at relatively low voltage with good memory retention [124]. The device properties demonstrated, however, seem to be questionable to justify the authors’ claims properly.

Further development has been made by de Leeuw et al. by fabricating a FeFET made of all organic components [125]. Besides ferroelectric and semiconducting layers, all three electrodes were made of a conducting polymer, poly(3,4- ethylenedioxythiphene) stabilized with polystyrene-4- sulphonic acid in a FeFET. The memory device with either unipolar p- or n-type semiconductor channel showed on/off drain current ratio of approximately 103 with the retention and the switching time of hours and 0.1-1 ms, respectively when operated at the voltage less than ± 15 V. A recent work by Naber et al has made an attempt to elucidate the mechanism

behind the observed drain current bistability in a FeFET containing a P(VDF-TrFE) layer [126]. The work clearly demonstrated that the bistability originates from switching between two states in which the ferroelectric gate dielectric is either polarized or depolarized.

2.3.4 INORGANIC SEMICONDUCTOR BASED

FEFETS

Oxide semiconductors are beneficial for a high performance FeFET device containing a P(VDF-TrFE) film due to their transparency as well as high carrier mobility. A top gate ZnO FeFET has been reported by Noh et al with a poly(4- vinylphenol) (PVP)/P(VDF-TrFE) double layer gate dielectric which shows remarkably reduced leakage current with the aid of the PVP buffer. The device exhibits a field effect mobility of 0.36 cm2/Vs and a large memory hysteresis in the transfer characteristics with the data retention longer than 2 h [127]. Graphene was also utilized as an active channel layer for a FeFET with a P(VDF-TrFE) thin film [128]. Similar to other semiconductors, the high and low resistance states of the graphene working channels were switched by controlling the polarization of the ferroelectric thin film using gate voltage sweep. The field effect mobility of graphene was measured of approximately 1500 cm2/Vs, rendering a FeFET a good candidate for high speed memory. The programming voltage reported was rather high of 80 V due to the P(VDF-TrFE) film of 700 nm in thickness.

2.3.5 SOLUBLE PENTACENE BASED FEFETS

We have developed a new type of non-volatile FeFET with single crystal triisopropylsilylethynyl pentacene (TIPS-PEN) active layer. A bottom gate FeFET was fabricated with thin P(VDF-TrFE) film gate insulator on which 1D ribbon type single crystal TIPS-PEN grown via solvent exchange method was positioned between Au source and drain electrode as shown in Figure 11a [129]. Post thermal treatment optimized the interface between flat single crystalline ab plane of TIPSPEN and polycrystalline P(VDF-TrFE) surface with characteristic needle-like crystalline lamellae. The reliable interface between the single crystal and P(VDF-TrFE) layer gave rise to not only high hysteresis ON/OFF ratio larger than 103 but also stable data retention capability consecutively measured over the period longer than 5x104 seconds in Figure 11b. The device operating at the gate voltage sweep of ±30V is environmentally stable for more than 200 days without additional passivation.

Single crystal TIPS-PEN active layer was further utilized in a FeFET containing a new ferroelectric layer of PVDF/PMMA blend prepared by the spin coating and subsequent melt-quenching [130]. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or the organic semi-conducting channel layer enabled us to fabricate a highly reliable FeFET device operating at the voltage as low as 15 V. For instance, with TIPS-pentacene single crystal as an active semi-conducting layer, a flexible FeFET showed a

clockwise I-V hysteresis with a drain current bistablility of a 103 and data retention time of more than 15 h at ±15 V gate voltage. Materials and device characteristics is summarized of FeFETs containing various semiconducting active channels and ferroelectric polymers in Table 2.

Figure 11. (a) An OM image of top view of a FeFET with single crystal TIPSPEN bridged between Au source and drain electrode. The inset shows a schematic of the FeFET device. (b) ISD-VG transfer curve of TIPS-PEN single crystal FeFET with bilayered P(VDF-TrFE)/PVP gate dielectric [129].

3 CHALLENGING ISSUES FOR MATERIALS AND PROCESS DESIGN

For high performance ferroelectric memory devices, first of all, a good quality film should be guaranteed which can not only form proper interfaces with other device component such as metal electrode and semiconductor but also at the same time maximize its ferroelectric properties. In the sense of highly performing ferroelectrics, one should take into account the semi-crystalline structure of a ferroelectric polymer film because the assembly of the ferroelectric polymer chains into a crystalline lattice and further to hierarchical morphological suprastructure mostly determines the collective ferroelectric properties of a device. The issues involved for this aspect include the control of crystal polymorphs, degree of crystallinity, crystal size and its distribution and crystal orientation. For instance, high b axis orientation of the ferroelectric P(VDF-TrFE) crystals parallel to applied electric field direction is of prime importance for a successful device performance with the degree of crystallinity as high as

possible. The large crystalline domains developed for high crystallinity, however, often result in very rough and inhomogeneous film surface which is in general undesirable for reliable device performance. For instance, in a FeFET device, a rough ferroelectric gate insulator frequently forms an unstable interface with a semi-conducting channel layer, leading to poor channel mobility and reliability [131, 132]. One design rule to overcome these problems may be to make the crystalline domains as small as possible while maintaining the same total high degree of crystallinity. An alternative approach to have a homogenous interface with heteromaterial surface is to have an interlayer inserted between ferroelectric and either metal or semiconductor layer. As will be shown next, interlayers turned out to have various roles in ferroelectric devices. For example, they are very effective for improving fatigue properties of a MFM capacitor. In addition, interlayers employed in FeFET devices significantly reduced the gate leakage current, leading to high on/off current ratio.

Another important requirement for realizing polymeric memory devices is the capability of micro/nano pattern formation to ensure high density integration per unit area [133]. The selective etching of material using a patterned mask is common in CMOS based memory fabrication. Ferroelectric polymer, however, is significantly damaged or alters its intrinsic properties under the harsh patterning conditions, which suggests that a new non-destructive pattern technique should be applied. Soft lithography is one of the highly plausible alternatives. In the next sections, various ways to control crystal polymorphs as well as crystal orientations will be first discussed of a ferroelectric polymer thin film for highly reliable ferroelectric memory devices. The subsequent section will deal with the attempts to improve the performance of a ferroelectric memory by employing functional interlayers. Finally, the current development in patterning a ferroelectric polymer film will be covered.

3.1 CONTROL OF POLYMORPHIC CRYSTALS OF PVDF FOR FERROELECTRIC THIN FILMS

When one considers PVDF as a ferroelectric layer, there are two important issues which should be additionally addressed of how effectively to achieve (1) ferroelectric β crystals with their all trans planar zigzag conformation (TTTT) (β provides the better polarization than either α or γ PVDF crystals) and

(2) a spin coated morphologically homogeneous thin film with a thickness less than 200 nm and very low surface roughness. Although many attempts have been made to fabricate β crystals of PVDF including mechanical stretching, electrical poling, addition of hygroscopic salts, epitaxy on KBr, control of cooling and heating rates as well as solvent evaporation and blending with poly(methylmethacrylate) (PMMA),[115, 134136] their applications for ferroelectric memory devices remain elusive mainly because films were too thick and too rough for low voltage operating memory applications requiring at least ±20 V for switching.

Wang et al has proposed a method for fabricating ultra thin melt-drawn film with β crystals by melting and recrystallization under carbon evaporated surface [137].

In addition, Kim et al have also reported that the addition of organically modified silicate (OMS) into PVDF film was very effective for fabricating β type ferroelectric films applicable for thin film MFM capacitors [138]. From the industrial point of view, spin coating is one of the most desirable methods for large area uniform film formation and thus provides a great benefit when it is incorporated in fabricating PVDF based devices. Our recent work has also shown PVDF thin films with polar γ crystals prepared by pressurizing spin cast thin films at certain temperature range [139]. The pressure induced polymorphic phase transition was evidenced by the remanent polarization and coercive voltage of approximately 6.0 μC/cm2 and 11 V, respectively measured in the pressurized PVDF films with 200 nm in thickness. It is still challenging to conveniently prepare uniform ferroelectric PVDF thin film with β crystals whose permanent polarization can switch at low voltage with high temperature stability. We have develop a method to fabricating ferroelectric β-type PVDF thin films on Au substrate by the humidity controlled spin casting combined with rapid thermal treatment [115]. Our method produces thin uniform ferroelectric PVDF film with ordered β crystals consisting of characteristic needle-like microdomains. A capacitor with a 160 nm thick ferroelectric PVDF film exhibits the remanent polarization and coercive voltage of approximately 7.0 μC/cm2 and 8 V, respectively with the

temperature stability up to 160 °C. A ferroelectric field effect transistor also shows a drain current bistablility of 100 at zero

gate voltage with ±20 V gate voltage sweep.

The melt and ice quenching of a thin PMMA/PVDF blend film spin coated on substrates turned out an effective way to form ferroelectric β PVDF crystals [130]. This allowed us to fabricate new type of ferroelectric polymer films with very low surface roughness and a remarkable polarization Pr of approximately 4.3 μC/cm2 as shown in Figure 12a. For example, a 100 nm thick PVDF/PMMA (80/20) films have been successfully utilized as a gate insulator of a FeFET employing a single crystal TIPS-PEN organic semiconductor. Such devices exhibited excellent p-type nonvolatility of IDS larger than 104 and a data retention of more than 15 hours at the programming voltage of ±15 V as demonstrated in Figure 12b.

3.2 CONTROL OF MOLECULAR AND

MICROSTRUCTURAL ORIENTATION OF

P(VDF-TrFE) CRYSTALS

Effective crystal orientation with respect to electric field direction is also of a prime importance for successful device realization. For PVDF and P(VDF-TrFE), the polarization is

optimized when the crystal b axis becomes parallel to electric field. A number of studies have dealt with a reduceddimension system in spin cast ferroelectric layers and found a significant decrease of remanent polarization and crystallinity of the copolymer of VDF and TrFE as the film thickness decreased. Naber et al overviewed the relationship between layer thickness and remanent polarization in spin cast P(VDFTrFE) capacitors, including their results, as a summary from the literature regarding the thickness scaling [75]. Even though the processing conditions and the measurement procedures for those plotted data are not the same, the abrupt decline of the remanent polarization measured in sub-100nm P(VDF-TrFE) films has been shown in Figure 13 (the refs. in the inset are relevant to the ref. [75]) and this behavior is attributed to the decrease of crystallinity in P(VDF-TrFE) thin films in most works. In the ultrathin film below 100 nm, it is figured out that the crystallinity diminishes due to the strong interaction between substrate and ferroelectric polymer.

film. The critical impact of crystal orientation on the polymer ferroelectrics is shown in the literature by Bune et al where ferroelectric properties were measured even in films of only two monolayers, fabricated by the LB technique [72].

The ferroelectric properties dependent upon crystal orientation were observed in particular when a film underwent the melt and recrsyatllization. We have reported that the ferroelectric polarization of a 200 nm thick P(VDF-TrFE) film measured at room temperature was significantly reduced upon melting and re-crystallization. The c axis of the crystals after melting and recrystallization was parallel to surface normal as well as the electric field applied and consequently renders b axis, polarization axis ineffective for dipole switching, leading to the very low Pr [78]. The crystal orientation dependent polarization was also investigated in Al/P(VDF-TrFE)/Au capacitors in which Au bottom electrode was treated with SAMs for controlling chemical nature of surface. In general a preferred crystal orientation observed on surfaces with polar nature is found to provide superior polarization [140].

Figure 12. (a) Plots of remanent polarization (Pr) (black) and RMS roughness (blue) as a function of the amount of the PMMA content in the blend films quenched and annealed at 150 °C. (b) ID-VG transfer curve of a single crystal TIPS-PEN FeFET with a thin PVDF/PMMA (80/20) gate insulator meltquenched and subsequently annealed on a PVP layer at 150 °C. The inset on the left depicts the schematic of the FeFET. The inset on the right in (b) shows an OM image of top view of the FeFET, visualizing the single crystal TIPSPEN bridged between Au source and drain electrode [130].

There however exists an argument on the reduction of Pr arising from the decrease of crystallinity when a film becomes thinner. Usage of a chemically neutral electrode such as Au gave rise to thickness-independent switching time and Pr in the thickness ranging from 50 to 500 nm. Our recent study also showed that the characteristic needle-like crystalline domains were evidenced even in a 30 nm thick P(VDF-TrFE)

Figure 13. Summary of the remanent polarization of spin coated P(VDF-TrFE) capacitors as a function on the ferroelectric layer thickness [75].

The microstructure composed of the characteristic 200 nm long and 40 nm wide crystalline lamellae typically nucleate randomly and grow as a polygranular texture in a P(VDFTrFE) film. Several techniques are currently used for inducing long range order of the microstructure of P(VDF-TrFE). They rely on the ability to couple an externally applied field to some molecular and/or supermolecular feature in the polymer and include crystallographic matching on a surface known as epitaxy[68,69,141], localized thermal gradient [142], and mechanical fields[136,143,144]. In spite of numerous previous studies, a single crystal-like P(VDF-TrFE) thin film with the crystal orientation optimized for electric field would be the most suitable for realization of high performance ferroelectric polymer memory. From industrial point of view, again a film would be better formed by spin coating with the thickness as thin as possible. We have reported two approaches based on ferroelectric polymer eptiaxy and mechanical shearing.

3.2.1 EPITAXY

The recent advances in synthesis of epitaxial pervoskite ferroelectrics are promising on silicon [145, 146]. Inorganic epitaxial ferroelectric films have been deposited on various appropriate single crystal substrates. For example, a carefully controlled MOCVD process has been widely utilized for fabricating epitaxial films of PZT, SBT, BLT, and BNT for different orientations which exhibit the properties very similar to those expected for bulk single crystals with square hysteresis loops and low coercive fields [146]. We have demonstrated the high throughput epitaxy of a thin P(VDF-TrFE) film on a molecularly ordered poly(tetrafluoroethylene) (PTFE) substrate based on spin coating method over the area of a few centimeter square. We employed a process developed by Wittmann and Smith based on fabrication thin polymer films on substrates by the friction force generated while a heated PTFE bar was slowly moved under pressure over a substrate. Molecularly arranged polymer chains well aligned along the moving direction acted as single crystal surface on which various polymers were epitaxially grown [147]. The lattice

match between (010)P(VDF-TrFE) and (100)PTFE results in b and c axis of P(VDF-TrFE) crystals preferentially

parallel to a and c of PTFE, respectively and consequently produces global ordering of the edge-on P(VDF-TrFE) crystalline lamellae aligned perpendicular to the rubbing direction of PTFE, its c- axis as shown in Figure 14 [148]. The epitaxially grown P(VDF-TrFE) film is successfully incorporated for arrays of ferroelectric capacitors that exhibit not only the significant reduction of ferroelectric thermal hysteresis but also the descent remanent polarization at very low effective operating voltage of ±5 V maintained to 88% of its initial value after number of fatigue cycles of 5x108 in the mode of bipolar pulse switching.

3.2.2 STATIC SHEAR

In order to fabricate single crystal-like P(VDF-TrFE) films spin coated with the thickness less than 200 nm, we utilized static shearing of the thin film with a labmade equipment modified from one for global microdomain orientation of thin poly(styrene-block- ethylenepropylene) copolymer films [149]. The apparatus we developed was capable of shearing hundred nanometer thick polymer films and enabled us to fabricate a globally ordered P(VDF-TrFE) thin film over the area larger than 1 cm2. An ordered film formed within 2 h had chain axis, c-axis, dominantly aligned along the shear direction with the crystalline lamellae uni-directionally oriented perpendicular to the shear as shown in Figure 15. In addition, a-axis of the crystals was aligned parallel to the surface normal with b-axis on the substrate. The best orientation was obtained in a 150 nm thick film sheared at 135 °C and gave rise to

the higher remanent polarization of approximately 6.9 µC/cm2 than that from a film simply annealed at 135 °C because of both the effective crystal orientation for polarization switching and the reduced microstructural defects. Table 3 summarizes various attempts to control either crystal polymorphs or crystal orientation in thin ferroelectric polymer films.

Figure 14. A bright field TEM micrograph of a P(VDF-TrFE) film highly oriented by epitaxial crystallization on friction transferred PTFE substrates. The red arrow indicates a chain axis of PTFE parallel to the rubbing direction. The inset displays a schematic representation of the microstructual orientation of P(VDF-TrFE) thin film with the crystalline lamellae of P(VDF-TrFE) aligned perpendicular to the chain axis of PTFE, rubbing direction of PTFE substrate. (b) A schematic of the molecular orientation of an epitaxially grown P(VDF-TrFE) on PTFE surface. P(VDFTrFE)/PTFE interface at the contact surface is seen along the chain

axes. The bcP(VDF-TrFE) plane is in contact with the acPTFE plane with the epitaxial relation of bP(VDF-TrFE)//aPTFE [148].

Figure 15. Tapping mode AFM image of a 150 nm thick P(VDF-TrFE) film sheared at 135 oC on Al substrate. The semi-crystalline lamellae are globally ordered perpendicular to the shear direction indicated by an arrow over very large area.

3.3 CONTROL OF INTERFACES OF

FERROELECTRIC POLYMERS WITH EITHER

METAL OR SEMI-CONDUCTOR

In memory elements, a ferroelectric polymer forms interfaces with metal electrode in a MFM structure and with both metal and semiconductor active layer in either a MFIS or a FeFET architecture. The physical and electrical properties of these heteromaterial interfaces are greatly related to the device performance and thus should be properly controlled for maximization of the ferroelectric device functions. The roughened surface should be smoothened out for reliable memory performance which arises from the semi-crystalline microstructure of a ferroelectric polymer film. In addition, various defect sites can accumulate undesired charges at a semi-conductor/ferroelectric interface. As consequence, many efforts have been made to improve the interfacial properties directly responsible for the device functions by modifying topology of a metal electrode and more frequently by incorporating either inorganic or organic interlayers.

Interlayers were originally introduced as buffer layers to prevent interdiffusion between semiconductor and ferroelectric oxide during high process temperature in inorganic MFIS and FeFET devices. In the case of the devices containing P(VDF-TrFE), there is no need to take into consideration of this problem due to the relatively low thermal

annealing temperature below 200 °C. Nevertheless various interlayers have been introduced in ferroelectric polymer memories with emphasis on their different roles including the modification of ferroelectric crystal orientation, the reduction of gate leakage and the improvement of field effect mobility of an organic semiconductor.

We improved high temperature stability of a MFM capacitor with a P(VDF-TrFE) layer by employing a topographical metallic bottom electrode based on etched Al which has a topographically nanostructured surface with hexagonal registry of the recessed hemi-spherical bowls of approximately 100 nm diameter [150]. Fairly large remanent polarization of 10µC/cm2 was obtained after annealing up to 185 °C with the etched Al electrode while the polarization rapidly dropped near the melting temperature of P(VDFTrFE) (~150 °C) with a flat Al electrode due to the alteration of crystal orientation [150]. A proper adaptation of the ferroelectric crystals on the topographic electrode is assumed responsible for the high temperature stability.

3.3.1 INTERLAYERS IN MFMS

The conducting polymer interlayer in a MFM capacitor containing a P(VDF-TrFE) layer plays an important role to alter not only a crystal orientation and crystallinity of P(VDF-

TrFE) but also capacitor performance. Naber et al. employed poly(3,4-ethylenedioxythiophene): poly(styrenesulfonicacid) (PEDOT:PSS) between a P(VDF-TrFE) layer and ITO electrode [76]. They observed that a Pr of 6.5 μC/cm2 was switched with only 5.2 V (80MV/m) with the switching time of 80ms which was 3 orders of magnitude faster than a similar capacitor with Al bottom electrode. Another polymeric conducting layer of thin polypyrrole-poly(styrene sulfonate) acid (Ppy-PSSH) film was inserted to form Ti/Ppy-PSSH/P(VDF-TrFE)/Ppy- PSSH/Ti structure. Xu et al. [74] have observed that the sandwiched structure shows the prominent ferroelectric properties where the coercive voltage, the remanent polarization and the switching time are 2.6 V, 8.6 μC/cm2 and 30μs with even 50 nm thickness of P(VDF-TrFE), respectively. The Ppy-PSSH layer increased the crystallinity as well as improved the crystal dipole orientation of P(VDF-TrFE). The same group has also reported the effective interlayer of PEDOT:PSSH inserted both top and bottom of a P(VDF-TrFE) in a MFM capacitor [151]. In particular, the fatigue properties of the capacitor were significantly improved due to the supply of charges needed for compensation of the dipoles to stabilize the domain during switching process. The work also demonstrated a high temperature operation of the capacitor at 60 °C.

We have employed self assembled monolayers (SAMs) between a P(VDF-TrFE) layer and Au bottom electrode and investigated in details the molecular and microstructure of semi-crystalline thin films as a function of both film thickness and surface property of the Au or SAM interlayer [140]. In all films, the c axis is oriented in the contact plane, that is, parallel to the substrate. We observed that the films deposited on bare Au and on polar SAMs are characterized by a (110) contact plane, whereas those deposited on CH3-terminated SAMs have a (100) contact plane, which implies that the P(VDF-TrFE) b axis of the unit-cell is either tilted at some 30° to the film surface normal, or lies in the plane of the film. The different unit-cell orientations of the films are manifested by different remanent polarizations when the films are submitted to relatively low voltages of 10-15 V, i.e. that remain below the coercive voltage in the thin films investigated. When the films are submitted to >20V, molecular reorientation in the films wipes out these structural differences to a significant extent. Interestingly however, the films produced on both polar and apolar substrates have densely populated contact planes. This implies that the sole reorientation of the chains by rotation on their axis under a coercive electric field, generates at best a structure in which the polar b axis is oriented at 30° to the electric field.

active layers, thermally grown SiO2 layer was dominantly utilized not only for understanding the device physics but also for improving device performance. Typical C-V hysteresis curves was clearly observed in metal/P(VDF- TrFE)/silicon-oxide/n-type silicon with highly ordered P(VDF-TrFE) thin film prepared by Langmuir-Blodgett

process as the gate voltage was cycled between ±25 V [99].

The MFIS devices based on SiO2 insulator, however, usually exhibits the gate voltage shifted C-V hysteresis curve with very low capacitance difference at 0 gate bias, which requires additional gate bias for optimizing memory bistability. A detailed investigation of this phenomenon by Lim et al [102] revealed that the polarization field direction against electric field and remnant polarization of ferroelectric polymer induced the flat band voltage shift. Furthermore, a recent work by Henkel et al [103] described the formation of an interfacial non-ferroelectric layer in a MFIS device with SiO2 interlayer which was responsible for reduced polarization value. By controlling both thicknesses P(VDF-TrFE) films and SiO2 buffer layer, they improved the data retention for more than 5 days from thin 100nm P(VDF-TrFE) with 30nm SiO2 layer but observed imprint and fatigue-like behavior when long-time measurements were performed.

Fujisaki et al [104] have suggested that an interlayer of a 3 nm thick Ta2O5 in a MFIS element with a P(VDF-TrFE) layer prevents effectively the intrinsic negative flat bandvoltage shift observed with SiO2 interlayer in the previous works. The Ta2O5 interlayer gave rise to a good memory performance of rectangular-shaped C-V hysteresis loops with a voltage sweep range of ±5 V. The maximum memory width was 4.7 V. In addition, a recent work by Lu et al [105] have demonstrated a low-voltage operation of MFIS device by introducing a HfTaO interlayer which has good match of dielectric constant with that of P(VDFTrFE). A wide memory window of 1.2 V was observed in a MFIS with 6 nm thick HfTaO insulating layer for the voltage sweep of ±3V. The device also exhibited the good data retention over 4 hours after a small programming voltage of 3V. The depolarization field generated by the interlayer, which should be minimized in order to achieve good memory retention properties, is less critical in this case because of the lower dielectric constant of P(VDFTrFE) than oxide ferroelectric materials.

Polymeric interlayers such as poly(4-vinylphenol) (PVP) and poly(vinyl alcohol) (PVA) have been employed in MFIS devices with a P(VDF-TrFE) film. Our results in particular suggest that PVP layer on a p-type Si channel effectively prevented the flat band shift observed in a device with SiO2. In addition, a 40 nm thick PVP layer allowed a low voltage operation less than 15 V with good data retention over 40 hours [152].

MFIS memory elements with ferroelectric P(VDF-TrFE) have been successfully combined with various interlayers in the recent studies. For MFIS devices with n- or p-type Si

In FeFET memory devices, the interlayer serves as the insulator to prevent gate current leakage between gate and drain which is a typical reason for poor memory