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74AHC_AHCT00.pdf

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NXP Semiconductors	74AHC00; 74AHCT00
	Quad 2-input NAND gate

11. Waveforms

nA, nB input		VM

GND

tPLH				tPHL

VOH

nY output		VM

VOL

001aah088

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. Input to output propagation delays

Table 8.

Measurement points

Type

Input

Output

74AHC00

0.5 × VCC

74AHCT00

1.5 V

0.5 × VCC

90 %

negative

pulse

10 %

GND

90 %

positive

pulse

GND 10 %

VCC

DUT

001aah768

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 7. Load circuitry for measuring switching times

74AHC_AHCT00_4

Product data sheet

Rev. 04 — 28 April 2008

7 of 14

NXP Semiconductors				74AHC00; 74AHCT00
					Quad 2-input NAND gate
Table 9.	Test data

Type		Input		Load		Test
		VI	tr, tf	CL
74AHC00		VCC	≤ 3.0 ns	15 pF, 50 pF		tPLH, tPHL
74AHCT00		3.0 V	≤ 3.0 ns	15 pF, 50 pF		tPLH, tPHL

74AHC_AHCT00_4

Product data sheet

Rev. 04 — 28 April 2008

8 of 14

NXP Semiconductors	74AHC00; 74AHCT00
	Quad 2-input NAND gate

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D		E	A
				X
	c
y		HE		v M A
		HE		v M A
Z
14	8
		Q
		A2	(A3)	A
		A1	(A3)	A
pin 1 index
				θ
		L p
1	7	L
1	7
e	w M	detail X
	bp

							0		2.5		5 mm

									scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT	A	A1	A2	A3	bp	c	D(1)	E(1)	e	HE		L	Lp	Q	v	w	y	Z (1)	θ
UNIT	max.	A1	A2	A3	bp	c	D(1)	E(1)	e	HE		L	Lp	Q	v	w	y	Z (1)	θ
	max.

mm	1.75	0.25	1.45	0.25	0.49	0.25	8.75	4.0	1.27	6.2	1.05		1.0	0.7	0.25	0.25	0.1	0.7
mm	1.75	0.10	1.25	0.25	0.36	0.19	8.55	3.8	1.27	5.8	1.05		0.4	0.6	0.25	0.25	0.1	0.3	8o
		0.10	1.25		0.36	0.19	8.55	3.8		5.8			0.4	0.6				0.3	8o
																			0o
inches	0.069	0.010	0.057	0.01	0.019	0.0100	0.35	0.16	0.05	0.244	0.041		0.039	0.028	0.01	0.01	0.004	0.028	0o
inches	0.069	0.004	0.049	0.01	0.014	0.0075	0.34	0.15	0.05	0.228	0.041		0.016	0.024	0.01	0.01	0.004	0.012

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT108-1

076E06

MS-012

99-12-27

03-02-19

Fig 8. Package outline SOT108-1 (SO14)

74AHC_AHCT00_4

Product data sheet

Rev. 04 — 28 April 2008

9 of 14

NXP Semiconductors	74AHC00; 74AHCT00
	Quad 2-input NAND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D		E	A
			X
	c
y		HE	v M A
		HE	v M A
Z
14	8
			Q
	A	2	(A3)
		2	A
pin 1 index		A1
			θ
			Lp
		L
1	7
	w M	detail X
	w M
e	bp

							0		2.5			5 mm

									scale
DIMENSIONS (mm are the original dimensions)

UNIT	A	A1	A2	A3	bp	c	D (1)	E (2)		e	HE		L	Lp	Q	v	w	y	Z (1)	θ
UNIT	max.	A1	A2	A3	bp	c	D (1)	E (2)		e	HE		L	Lp	Q	v	w	y	Z (1)	θ
	max.

mm	1.1	0.15	0.95	0.25	0.30	0.2	5.1	4.5	0.65		6.6	1		0.75	0.4	0.2	0.13	0.1	0.72	8o
mm		0.05	0.80		0.19	0.1	4.9	4.3			6.2			0.50	0.3				0.38	0o
		0.05	0.80		0.19	0.1	4.9	4.3			6.2			0.50	0.3				0.38	0o

Notes

1.Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2.Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT402-1

MO-153

99-12-27

03-02-18

Fig 9. Package outline SOT402-1 (TSSOP14)

74AHC_AHCT00_4

Product data sheet

Rev. 04 — 28 April 2008

10 of 14

NXP Semiconductors	74AHC00; 74AHCT00
	Quad 2-input NAND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

D B A

	A
E	A1
E	c
terminal 1	detail X
terminal 1
index area

terminal 1	e1					C
terminal 1	e1
index area					y1 C	y
e	b	v	M C A B		y1 C	y
2		w	M	C
2		6
L
1		7
Eh		e
14		8
13		9
	Dh					X
						X
0		2.5				5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT	A(1)	A1	b	c	D(1)	Dh	E(1)	Eh	e	e1	L	v	w	y	y1
	max.
mm	1	0.05	0.30	0.2	3.1	1.65	2.6	1.15	0.5	2	0.5	0.1	0.05	0.05	0.1
		0.00	0.18		2.9	1.35	2.4	0.85			0.3

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT762-1

- - -

MO-241

- - -

02-10-17

03-01-27

Fig 10. Package outline SOT762-1 (DHVQFN14)

74AHC_AHCT00_4

Product data sheet

Rev. 04 — 28 April 2008

11 of 14

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