74AHC00; 74AHCT00
Quad 2-input NAND gate
Rev. 04 — 28 April 2008 |
Product data sheet |
1. General description
The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. JESD7-A.
The 74AHC00; 74AHCT00 provides the quad 2-input NAND function.
2. Features
nBalanced propagation delays
nAll inputs have Schmitt-trigger actions
nInputs accept voltages higher than VCC
nInput levels:
uFor 74AHC00: CMOS level
uFor 74AHCT00: TTL level
n ESD protection:
uHBM EIA/JESD22-A114E exceeds 2000 V
uMM EIA/JESD22-A115-A exceeds 200 V
uCDM EIA/JESD22-C101C exceeds 1000 V
nMultiple package options
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
3.Ordering information
Table 1. Ordering information
Type number |
Package |
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Temperature range |
Name |
Description |
Version |
74AHC00 |
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74AHC00D |
−40 °C to +125 °C |
SO14 |
plastic small outline package; 14 leads; |
SOT108-1 |
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body width 3.9 mm |
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74AHC00PW |
−40 °C to +125 °C |
TSSOP14 |
plastic thin shrink small outline package; 14 leads; |
SOT402-1 |
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body width 4.4 mm |
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74AHC00BQ |
−40 °C to +125 °C |
DHVQFN14 |
plastic dual in-line compatible thermal enhanced very |
SOT762-1 |
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thin quad flat package; no leads; 14 terminals; |
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body 2.5 × 3 × 0.85 mm |
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