NXP Semiconductors

74AHC08; 74AHCT08

Quad 2-input AND gate

11. Waveforms

VI

nA, nB input

VM

GND

tPHL

tPLH

VOH

nY output

VM

VOL

mna224

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays

Table 8.

Measurement points

Type

Input

Output

VM

VM

74AHC08

0.5VCC

0.5VCC

74AHCT08

1.5 V

0.5VCC

74AHC_AHCT08_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 14 November 2007

7 of 14

NXP Semiconductors

74AHC08; 74AHCT08

Quad 2-input AND gate

VI

90 %

tW

negative

VM

VM

pulse

0 V

10 %

tf

tr

VI

tr

tf

90 %

positive

VM

VM

pulse

10 %

0 V

tW

VCC

VCC

VI

VO

RL S1

PULSE

DUT

open

GENERATOR

RT

CL

001aad983

Table 9.

Test data

Type

Input

Load

S1 position

VI

tr, tf

CL

RL

tPHL, tPLH

tPZH, tPHZ

tPZL, tPLZ

74AHC08

VCC

≤ 3.0 ns

15 pF, 50 pF

1 kΩ

open

GND

VCC

74AHCT08

3.0 V

≤ 3.0 ns

15 pF, 50 pF

1 kΩ

open

GND

VCC

74AHC_AHCT08_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 14 November 2007

8 of 14

NXP Semiconductors

74AHC08; 74AHCT08

Quad 2-input AND gate

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

c

y

HE

v M A

Z

14

8

Q

A2

(A3)

A

A1

pin 1 index

θ

L p

1

7

L

e

w M

detail X

bp

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

A

A1

A2

A3

bp

c

D(1)

E(1)

e

HE

L

Lp

Q

v

w

y

Z (1)

θ

max.

mm

1.75

0.25

1.45

0.25

0.49

0.25

8.75

4.0

1.27

6.2

1.05

1.0

0.7

0.25

0.25

0.1

0.7

0.10

1.25

0.36

0.19

8.55

3.8

5.8

0.4

0.6

0.3

8o

0o

inches

0.069

0.010

0.057

0.01

0.019

0.0100

0.35

0.16

0.05

0.244

0.041

0.039

0.028

0.01

0.01

0.004

0.028

0.004

0.049

0.014

0.0075

0.34

0.15

0.228

0.016

0.024

0.012

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT108-1

076E06

MS-012

99-12-27

03-02-19

74AHC_AHCT08_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 14 November 2007

9 of 14

NXP Semiconductors

74AHC08; 74AHCT08

Quad 2-input AND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

HE

v M A

Z

14

8

Q

A

2

(A3)

A

pin 1 index

A1

θ

Lp

L

1

7

w M

detail X

e

bp

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

A1

A2

A3

bp

c

D (1)

E (2)

e

HE

L

Lp

Q

v

w

y

Z (1)

θ

max.

mm

1.1

0.15

0.95

0.25

0.30

0.2

5.1

4.5

0.65

6.6

1

0.75

0.4

0.2

0.13

0.1

0.72

8o

0.05

0.80

0.19

0.1

4.9

4.3

6.2

0.50

0.3

0.38

0o

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT402-1

MO-153

99-12-27

03-02-18

74AHC_AHCT08_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 14 November 2007

10 of 14

NXP Semiconductors

74AHC08; 74AHCT08

Quad 2-input AND gate

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

A

E

A1

c

terminal 1

detail X

index area

terminal 1

e1

C

index area

y1 C

y

e

b

v

M C A B

2

w

M

C

6

L

1

7

Eh

e

14

8

13

9

Dh

X

0

2.5

5 mm

UNIT

A(1)

A1

b

c

D(1)

Dh

E(1)

Eh

e

e1

L

v

w

y

y1

max.

mm

1

0.05

0.30

0.2

3.1

1.65

2.6

1.15

0.5

2

0.5

0.1

0.05

0.05

0.1

0.00

0.18

2.9

1.35

2.4

0.85

0.3

OUTLINE

REFERENCES

EUROPEAN

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

PROJECTION

SOT762-1

- - -

MO-241

- - -

02-10-17

03-01-27

74AHC_AHCT08_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 14 November 2007

11 of 14