NXP Semiconductors |
74AHC08; 74AHCT08 |
|
Quad 2-input AND gate |
4. Functional diagram
|
|
|
|
|
|
|
|
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
& |
|
3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
1A |
3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
1Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
1B |
|
|
|
4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
4 |
2A |
|
|
|
|
5 |
& |
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
2Y |
|
|
|
|
|
|
A |
|
|
|
|
|
|
|
|
|
|
|
|||
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
2B |
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
9 |
3A |
|
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
10 |
3B |
3Y |
|
|
|
9 |
& |
|
8 |
|
B |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
10 |
|
|
|
|
|
|
|
|
|
|
mna221 |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
12 |
4A |
|
|
|
|
|
|
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
4Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
13 |
4B |
|
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
& |
|
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
mna222 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mna223 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Fig 1. Logic symbol |
|
|
Fig 2. |
IEC logic symbol |
|
|
Fig 3. Logic diagram (one gate) |
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5.Pinning information
5.1Pinning
|
|
|
|
|
|
1A |
1 |
|
|
14 |
VCC |
|
|
|
|
|
|
1B |
2 |
|
|
13 |
4B |
|
|
|
|
|
|
1Y |
3 |
|
|
12 |
4A |
|
|
|
08 |
|
|
2A |
4 |
11 |
4Y |
||
|
|
|
|
|
|
2B |
5 |
|
|
10 |
3B |
|
|
|
|
|
|
2Y |
6 |
|
|
9 |
3A |
|
|
|
|
|
|
GND |
7 |
|
|
8 |
3Y |
|
|
|
001aac945 |
|
|
|
|
|
|
|
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1 |
|
1A |
CC |
|
|
|
V |
|
|
||
index area |
|
|
|
||
|
|
|
|
|
|
1B |
2 |
1 |
14 |
13 |
4B |
|
|
||||
1Y |
3 |
|
|
12 |
4A |
|
|
||||
2A |
4 |
|
08 |
11 |
4Y |
2B |
5 |
GND(1) |
10 |
3B |
|
|
|
|
|
||
2Y |
6 |
|
|
9 |
3A |
|
|
7 |
8 |
|
|
|
|
|
|
|
|
|
|
GND |
3Y |
|
001aac946 |
|
|
|
|
|
|
Transparent top view
(1)The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 5. Pin configuration DHVQFN14
74AHC_AHCT08_3 |
© NXP B.V. 2007. All rights reserved. |
Product data sheet |
Rev. 03 — 14 November 2007 |
2 of 14 |