The Outside World

CHAPTER 10

The Real World

Up to this point we have mainly concentrated on how the software has interacted with the processor’s internal registers and Data memory. Now, as a prelude to how the MCU relates to its internal peripheral devices and hence monitors and controls its external environment, i.e. the real world outside its pins, we need to look at external support issues, such as power supply requirements, clocking and resetting.

After reading this chapter you will:

•Be familiar with the permitted range of power supply and input/output voltages.

•Distinguish between quiescent and dynamic power dissipation and recognize that the latter is directly proportional to both frequency and to the square of the supply voltage.

•Be aware of how the sleep mode is invoked and exited, and its e ect on the processor.

•Understand the basics of the integral clock oscillator.

•Know how the PIC’s configuration can be set up during programming.

•Understand the various nuances of the Reset process.

Figure 10.1 gives the external view of some typical PIC family members, ranging from the minuscule 8-pin 12-bit PIC12C508/9, which features one 5-bit general-purpose parallel I/O port, a Timer and 12 Kbyte Program store and 25/41 file registers through to the jumbo 40-pin 14bit PIC16F877 which has a 8 Kbyte flash memory Program store, 368 file registers, 33 bits of parallel I/O, three Timers, a 10-bit A/D converter, several serial port formats and a 256-byte EEPROM Data module. We are going to mainly concentrate on the 18-pin PIC16F83/41 and the 40-pin PIC16C74, but most of the characteristics are similar across all PIC families. Where relevant, other family members will be used as the exemplar; particularly the PIC16C7X and PIC16F87X devices.

All members of the PIC family will operate typically with a supply voltage VDD of nominally 5 V. The standard PIC16F84 can operate over

1The PIC16F83 is identical to the PIC16F84 but has 50% less Program memory and 36 instead of 68 file registers. The latter is currently available as the PIC16F84A with minor enhancements.

256 The Quintessential PIC Microcontroller

Fig. 10.2 Typical supply current versus clocking frequency.

proportional to the square of the supply voltage, so halving VDD from 5 V to 2.5 V should quarter the power dissipation VDD × IDD.3

The dynamic power dissipation derived above should be added to that due to the quiescent current that the device consumes when the clocking rate is dropped to zero. In the case of the PIC16F84 this power-down current IPD is quoted in the data sheet as typically 1 µA with a VDD of 4 V and 16 µA worst case. The PIC12C5XX has equivalent values quoted at VDD of 3 V of 0.3 µA and 5 µA respectively.

Of course not clocking a digital circuit is rather unproductive. All PIC families feature a Sleep mode which e ectively turns o the internal clock oscillator. This switch is actioned in software using the sleep instruction. Once asleep the contents of the Data store are retained pro-

3This is why most current microprocessors used as the PC CPU, such as the Intel Pentium III, are powered at under 3 V rather than the standard 5 V of older devices.

258 The Quintessential PIC Microcontroller

lowed by a clrwdt (CLeaR WatchDog Timer) instruction. Checking the appropriate Interrupt flag in the INTCON register will determine if the source of the awakening was an interrupt.

Whatever the source of the awakening there will be a delay of 1024 clock cycles fOSC before processing of the instruction following the sleep breakpoint. This is to ensure that the crystal clock oscillator has started up and stabilized. This oscillator startup delay, illustrated in Fig. 10.7, is not implemented if the PIC is using a resistor-capacitor clock mode of Fig. 10.4(b) and itemized in Table 10.2.

The power down current IPD is lower when the Watchdog timer is not enabled; for example; for the PIC16F84 IPD is quoted as typically 1.0 µA (16 µA maximum) and 7 µA (28 µA maximum) with the Watchdog timer disabled/enabled respectively. Figures are given for a VDD of 4 V I/O ports set to input and pins tied to either VDD or VSS (usually ground).

All members of the PIC family have an integral oscillator circuit which when completed with timing elements provide the internal clocking waveforms shown in Fig. 4.4 on page 87. The PIC12C5XX family have an optional internal RC timing elements giving a nominal 4 MHz clocking rate and allow the oscillator pins OSC1 and OSC2 to used as general-purpose parallel input/output lines – GP4 and GP5 in Fig. 10.1(a).

VDD

Fig. 10.4 Typical oscillator configurations.

The PIC16CXXX family can be operated in one of four di erent oscillator modes. These are:

• LP (Low Power) for crystal timing elements below around 200 kHz, eg. a 32.768 kHz watch crystal.

•XT for both crystals and ceramic resonators up to 4 MHz.

•HS for high speed crystals and ceramic resonators above 4 MHz.

•RC for low cost external resistor/capacitor timing elements.

The 12C5XX family members call the RC mode EXTRC (EXTernal RC) to distinguish this from the INTRC (INTernal RC) mode.

260 The Quintessential PIC Microcontroller

The PIC125XX family have integral RC components which give a nominal 4 MHz clock rate. This releases the OSC1 pin for use as a generalpurpose port input/output pin GP5. The actual clocking rate can be varied slightly by software by means of a calibration SPR file register.

PICs in the RC/EXTRC mode have the system clock (FOSC/4) available at OSC2 which can be bu ered and used as a system clock to synchronize other components or PICs. In the PIC125XX family this facility may be disabled and the OSC2 pin used as a general-purpose port I/O pin GP4.

Our discussion on the configuration of the on-board oscillator covered four modes. Besides the oscillator modes, the Watchdog timer may be enabled or disabled and various other options chosen depending on the family device. For the particular case of the PIC16F83/4 there are four main modes, the oscillator having four submodes.

•Four oscillator submodes.

•Watchdog timer enable/disable.

•Power-up timer enable/disable.

•Code protection enable/disable.

These modes can be configured by raising the MCLR pin to 13 V which places the PIC device into its Program/Verify mode; see Fig. 10.5(a). In this state, outside circuitry, usually the device programmer, has access to the Program store and can burn in the application code. The Device programmer also has access to certain private Program store locations which are not visible when the PIC is running normally. Specifically, the mid-range PIC family reserve ‘secret’ location 2007h as their configuration word.6

Setting each bit, sometimes known as a fuse, in the configuration word to the appropriate value ensures that when the MCU is in its normal running mode the clock oscillator and other facilities will be configured appropriately. All PICs have the fuses shown in Fig. 10.5(b) but they may be disposed di erently and additional configuration options may be supported depending on the family member’s architecture.

We will look at the Power-up timer on page 264 and Watchdog timer in Chapter 13. Here we will consider code protection. Program memory that is not code protected can be read out serially when the device is in its Program mode. This is intended to allow the device programmer to verify the correct state of the code that has just been burnt into the Program store – see Fig. 16.4 on page 472. If all the CP fuse bits are cleared then this facility is blocked. This gives a measure of security protection against any attempt to copy software. Once programmed the CP bits cannot be subsequently erased even in windowed or EEPROM Program store devices. For this reason Microchip do not recommend using this

6The area of Program memory beyond the user Program store space belongs to the special test/configuration memory space 2000h–3FFFh which can be accessed only during external programming.

Fig. 10.5 Configuration word for the PIC16F83/4.

feature for such devices when being used for prototyping. Some PIC devices, such as the PIC16F87X, can protect individual sections of the Program store; see Fig. 15.7 on page 445.

Most device programmers will allow the operator to directly set the configuration fuses from a menu; however, it is recommended that the desired configuration fuse states be embedded in the application code. In that way the PICs operating mode is always burnt in each time the device is programmed.

As an example, consider a PIC16F83/4 which is to have the following configuration:

Oscillator in XT mode

Bits 1:0 = 01

Watchdog timer o

Bit 2 = 0

Power-up timer on

Bit 3 = 0

No code protection

Bits 13:4 = 1111111111

Then the directive

__config b’11111111110001’ ; or 3FF1h

in the assembly-level source file will create the line of machine code:

:02 400E 00 F13F 80

to the format described on page 206.7 At programming time this will set the fuses in 2007h accordingly. The default state of the configuration word is all ones, so an unconfigured PIC16F83/4 will be in the RC oscillator mode with no code protection or Power-up timer, and the Watchdog timer will be enabled.

7Remember the byte address 400Eh is twice the byte address equivalent 2007h and words are presented least-significant byte first.

262 The Quintessential PIC Microcontroller

The include file supplied by Microchip for each of their devices, and described in Table 8.4 on page 209 will have mnemonics for the bit patterns for each configuration mode supported by that PIC. These are designed to be ANDed together to give the composite 14-bit configuration word. Using this technique gives for our example:

__config _XT_OSC & _WDT_OFF & _PWRTE_ON & _CP_OFF

which gives exactly the same machine code but is more obvious and therefore less error prone. It is also more portable in that altering the include file is all that needs to be done when changing to an alternative processor, which may have a di erent arrangement of bits in its configuration word.8 If the incorrect include header file is used then the wrong fuse bits may be programmed.

C compilers will have a similar mechanism for programming the configuration fuses. For instance, the CCS compiler uses the directive #fuses at the top of the file. For our example this is:

#fuses XT,NOWDT,PUT,NOPROTECT

In order to start up reliably a MCU must come out of its non-powered state in an orderly manner; as it were, up and running. All PIC MCUs have an MCLR (Master CLeaR) pin which can be used in conjunction with an external switch to manually reset the device, as shown in Fig. 10.6(a). Provided that MCLR remains below 0.2VDD the device will remain halted (in Phase Q1 of the internal clock cycle – see Fig. 4.4 on page 87). In order to be recognized as a legitimate reset action MCLR must be low for at least 100 ns – see Example 10.2. The value 33 kΩ is the maximum recommended pull-up resistor to ensure that leakage current flow from VDD when the switch is open will not drop below 0.85VDD. The maximum leakage IIL into MCLR is given as ±5 µA for an input voltage range VSS ≤ MCLR ≤ VDD. The 100 Ω resistor gives a measure of protection by limiting current if a negative-going noise spike breaks down the input protection diodes.

When MCLR is logic 1 (i.e. ≥ 0.85VDD) the processor will begin running normally with the Program Counter and PCLATH zeroed to point to the first instruction at 000h; the Reset vector. In addition, the three Status register bank page bits (IRP, RP1 & RP0) are zeroed, forcing the processor to see data in Bank 0. If MCLR is used to awaken the processor from its Sleep state; TO will be 1 (no Watchdog time out) and PD will be 0 (processor was powered down), otherwise these bits will be unchanged. In all cases the Status register’s code condition flags remain unchanged. The e ect of resetting on the SPRs is summarized in Table 10.1.

8Even such close relatives as the PIC16C74 and PIC16C74A/B have di ering fuse dispositions, so it is essential to use the exact correct header file!.

10. The Real World 263

Table 10.1: PIC16F83/4 Special-Purpose Register file reset summary.

Bank 1

80h INDF Dummy location used for Indirect addressing (not a physical register)

Fig. 10.6 Manually resetting the PIC.

10. The Real World 265

2.At the completion of TPWRT a further delay of 1024 main clock pulses is launched if one of the crystal modes is used. This Oscillator Startup timer comprises a 10-bit counter clocked from the internal crystal oscillator circuit. It ensures that the main oscillator has started up

and is functioning correctly before processing begins. TOST is dependent on the crystal frequency; for example, a 32 kHz crystal will give a minimum 32 ms delay whilst a 10 MHz configuration gives a 102 µs delay. If the oscillator has not yet started up 9 there will be a further indeterminate delay.This delay is not implemented whenever the PIC is in its RC clock mode.

The TOST delay is also invoked when the MCU awakens from a Sleep state; again to ensure that the crystal oscillator restarts and is running normally before processing commences.

3.Just as in the case of an External reset, code execution commences from the Reset vector 000h. However, unlike the latter which does not alter the TO and PD bits, a Power-on reset sets both Status bits to their inactive state.

The power-on sequence for various situations is summarized in Table 10.2.

Table 10.2: Power-up reset and sleep timeouts.

Where a system does not need a Manual reset, MCLR may be tied directly to VDD. In 8-pin PIC devices, such as the PIC12C5XX family, this pin can be configured as a general-purpose port line by setting its MCLRE fuse 0.

It is possible that the onset of the PIC’s power supply is so slow that either the internal Power-up reset pulse is not generated, or even if it

is VDD does not reach its specified operating level after the TPWRT and TOST delays. This is generally 4 V for normal (i.e. not low-voltage) version

devices not operating in the HC crystal mode and 4.5 V for this highspeed operation. In this case the PIC may start execution in an erratic

932 kHz crystal oscillators have a typical start-up time of 1–2 seconds. Crystal oscillators ≥ 100 kHz have a typical start-up time of less than 10–20 ms and ceramic resonators are typically less than 1 ms. Times are voltage dependent.

266 The Quintessential PIC Microcontroller

manner or not at all. Where the reliability of the internal Power-up circuitry is in doubt, additional circuitry may be added to hold MCLR low when the power is first applied for long enough to ensure that the part does not come out of Reset until VDD has reached its operating range. The circuit in Fig. 10.6(b) is designed to hold MCLR low long enough to allow the supply to settle. The value of capacitor should be chosen so that the time constant CR is several times greater than that taken by the power supply to stabilize. With the resistance given, a 2.2 µF capacitor will give a time constant of approximately 100 ms. More details are given in Microchip’s application notes AN522: Power-up Considerations and AN607: Power-up Trouble Shooting.

It is also possible to reset the PIC with the Watchdog timer timing out. In this situation the processor will immediately begin code execution from the Reset vector and also clear the TO Status flag (active) and set the PD flag (not active). A Watchdog time-out when the processor is asleep will cause code execution to commence at the instruction following the sleep instruction after a delay of TOST if in a crystal mode. This time both TO and PD Status bits will be zeroed (active).

A summary of the various reset conditions is given in Table 10.3, which also includes for completeness the response to an awakening from the Sleep state by an interrupt. A Power-on reset will set both TO and PD flags (inactive), whereas a Manual reset will leave these bits unchanged. TO will be activated (0) when a Watchdog time-out occurs and deactivated (1) when a clrwdt or sleep instruction is executed. clrwdt also deactivates PD which is active after a sleep instruction. Both these status flags are read-only; that is they cannot explicitly be altered by instructions such as bsf.

Resetting zeros the Program counter (the Reset vector) and the various banking bits, such as RP0. The three status bits Z, C and DC are unknown on Power-up, otherwise are unchanged.

Table 10.3: Reset conditions.

X Not known: U Unchanged

268 The Quintessential PIC Microcontroller

an A or B su x added;10 for example, the PIC16C64/74 becomes the PIC16C64A/74A.

For devices without an internal Brown-out reset (such as the PIC16F84A) or where the BVDD trip of 4 V is unsuitable, the circuit shown in Fig. 10.8(b) is proposed as an external Brown-out circuit. Discuss its operation.

Solution

In the situation where VDD is 5 V or above, the Zener diode will conduct through RZ, holding the base resistor RB at 3.6 V. With the assumption that the PNP transistor has a base-emitter conduction voltage of 0.7 V then the base current (3.610−30.7 = 0.29 mA) is su cient to turn the transistor on and

MCLR is close to VDD.

When VDD drops below 3.6 + 0.7 V then there is no longer su cient potential to maintain the 0.7 V base-emitter bias and the transistor turns o with a consequent collector current of zero. In this situation MCLR is at earth potential and the device is held in Reset as desired. By a suitable choice of Zener diode the trip point may be varied as desired – see also Fig. 10.9.

Example 10.2

The data sheet for the PIC16F83/4 indicates that the minimum duration of the low state on the MCLR pin that will be recognised as a valid Reset is 100 ns. Can you think of problems that might arise as a consequence of this time sensitivity?

Solution

In a noisy environment erratic operation may occur with narrow pulses occasionally resetting the device seemingly at random. In such situations, low-pass filtering should be placed on the MCLR pin. Typically, a 1 nF highfrequency capacitor physically adjacent to MCLR together with a 10 kΩ pull-up resistor will su ce. The power supply should be well decoupled at the PIC’s power supply pins.

Newer PIC devices, such as the PIC16C64A/74A and 16F84A, have MCLR filters internally added. This master clear filter gives an e ective increase in the MCLR minimum duration from 100 ns to 2 µs.

Self-assessment questions

10.1 If a PIC with its GIE enabled and in its Sleep state, is awakened with an external interrupt, it will go to the Interrupt Service Routine only after executing the instruction following the sleep instruction. How

10Uncharacteristically the PIC16C71 becomes the PIC16C711.