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eZ80® CPU Registers in ADL Mode

In ADL mode, the BC, DE, HL, IX and IY registers are 24 bits long for multibyte operations and indirect addressing. The most significant bytes (MSBs) of these 3 multibyte registers are designated with a U to indicate the upper byte. For example, the upper byte of multibyte register BC is designated BCU. Thus, the 24-bit BC register in ADL mode is composed of the three 8-bit registers {BCU, B, C}. Likewise, the upper byte of the IX register is designated IXU. The 24-bit IX register in ADL mode is composed of the three 8-bit registers {IXU, IXH, IXL}.

Note: None of the upper bytes (BCU, DEU, IXU, etc.) are individually accessible as standalone 8-bit registers.

MBASE is not used for address generation in ADL mode; however, it can only be written in ADL mode. The Program Counter is 24 bits long, as is SPL. IEF1, IEF2, ADL, and MADL are single bit flags.

The CPU registers and bit flags during Z80 mode operation are indicated in Tables 3 and 4. Reset states are detailed in Table 5.

Table 3. CPU Working Registers in ADL Mode

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Table 4. CPU Control Registers and Bit Flags in ADL Mode

Control Registers and Bit Flags

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Table 5. CPU Register and Bit Flag Reset States (Continued)

eZ80® CPU Status Indicators (Flag Register)

The Flag register (F and F’) contains status information for the CPU. The bit position for each flag is indicated in Table 6.

Table 6. Flag Register Bit Positions

where:

C=Carry Flag

N=Add/Subtract Flag

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P/V=Parity/Overflow Flag

H=Half-Carry Flag

Z=0 Flag

S=Sign Flag

X=Not used

Each of the two CPU flag registers contain six bits of status information that are set or reset by CPU operations. Bits 3 and 5 are not used. Four of these bits are testable (C, P/V, Z and S) for use with conditional jump, call or return instructions. Two flags are not testable (H, N) and are used for BCD arithmetic.

Carry Flag (C)

The Carry Flag bit is set or reset, depending on the operation that is performed. For ADD instructions that generate a carry and SUBTRACT instructions that generate a borrow, the Carry flag is set to 1. The Carry flag is reset by an ADD that does not generate a carry, and a subtract that does not generate a borrow. This saved carry facilitates software routines for extended precision arithmetic. Also, the DAA instruction sets the Carry flag to 1 if the conditions for making the decimal adjustment are met.

For the RLA, RRA, RLC and RRC instructions, the Carry flag is used as a link between the least significant bit (lsb) and most significant bit (msb) for any register or memory location. During the RLCA, RLC m and SLA m instructions, the carry contains the last value shifted out of bit 7 of any register or memory location. During the RRCA, RRC m, SRA m and SRL m instructions, the carry contains the last value shifted out of bit 0 of any register or memory location. For the logical instructions AND A s, OR A s, and XOR A s, the carry is reset. The Carry flag can also be set (SCF) and complemented (CCF).

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Add/Subtract Flag (N)

The Add/Subtract (N) flag is used by the decimal adjust accumulator instructions (DAA) to distinguish between ADD and SUBTRACT instructions. For all ADD instructions, N is set to 0. For all SUBTRACT instructions, N is set to 1.

Parity/Overflow Flag (P/V)

The Parity/Overflow (P/V) flag is set or reset, depending on the operation that is performed. For arithmetic operations, this flag indicates an overflow condition when the result in the accumulator is greater than the maximum possible number (+127) or is less than the minimum possible number (–128). This overflow condition can be determined by examining the sign bits of the operands.

For addition, operands with different signs never causes overflow. When adding operands with like signs where the result yields a different sign, the overflow flag is set to 1, as indicated in Table 7.

Table 7. Overflow Flag Addition Settings

The two numbers added together result in a number that exceeds +127 and the two positive operands result in a negative number (–95), which is incorrect. Thus, the Overflow flag is set to 1.

For subtraction, overflow can occur for operands of unlike signs. Operands of like signs never causes overflow, as indicated in Table 8.

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Table 8. Overflow Flag Subtraction Settings

The minuend sign is changed from positive to negative, returning an incorrect difference. Thus, overflow is set to 1. Another method for predicting an overflow is to observe the carry into and out of the sign bit. If there is a carry in and no carry out, then overflow occurs.

This flag is also used with logical operation and rotate instructions to indicate the parity of the result. The number of 1 bits in a byte are counted. If the total is odd, then odd parity (P=0) is flagged. If the total is even, then even parity (P=1) is flagged.

During search instructions (CPI, CPIR, CPD, CPDR) and block transfer instructions (LDI, LDIR, LDD, LDDR), the P/V flag monitors the state of the byte count register (BC). When decrementing, the byte counter results in a 0 value and the flag is reset to 0; otherwise the flag is logical 1.

During LD A, I and LD A, R instructions, the P/V flag is set to 1 with the contents of the interrupt enable flip-flop (IEF2) for storage or testing. When inputting a byte from an I/O device, IN r,(C), the flag is adjusted to indicate the parity of the data.

The P/V flag is set to 1 to indicate even parity, and cleared to 0 to indicate odd parity.

Half-Carry Flag (H)

The Half-Carry flag (H) is set or reset, depending on the carry and borrow status between bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the decimal adjust accumulator instruction (DAA) to correct the result of a packed BCD addition or subtraction. The H flag is set to 1 or reset to 0, as indicated in Table 9.

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Table 9. H Flag Settings

Zero Flag (Z)

The Zero flag (Z) is set to 1 if the result generated by the execution of certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to 1 if the resulting byte in the accumulator is 0. If the byte is not 0, the Z flag is reset to 0.

For compare instructions, the Z flag is set to 1 if the value in the accumulator is the same as the data it is being compared against. When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit (see the BIT b, r instruction.

When inputting or outputting a byte between a memory location and an I/O device (for example, INI, IND, OUTI and OUTD), the B register is decremented. If the result of this decrement is 0 (that is, B–1 = 0), then the Z flag is set to 1. Otherwise, the Z flag is reset (cleared to 0). Also, for byte inputs from I/O devices using IN r,(C), the Z flag is set to 1 to indicate a zero-byte input.

Sign Flag (S)

The Sign flag stores the state of the most significant bit of the accumulator (bit 7). When the CPU performs arithmetic operations on signed numbers, binary two’s-complement notation is used to represent and process numerical information. A positive number is identified by a 0 in bit 7. A negative number is identified by a 1. The binary equivalent of the magnitude of a positive number is stored in bits 0–6 for a total range of 0–127. A negative number is represented by the two’s-complement of the equivalent positive number. The total range for negative numbers is –1 to –128.

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When inputting a byte from an I/O device to a register, IN r,(C), the S flag indicates either positive (S=0) or negative (S=1) data.