eZ80® CPU User Manual

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Memory Modes

The eZ80® CPU is capable of operating in two memory modes: Z80 mode and ADL mode. For backward compatibility with legacy Z80 programs, the CPU can operate in Z80 MEMORY mode with 16-bit addresses and 16-bit CPU registers. For 24-bit linear addressing and 24bit CPU registers, the CPU operates in ADDRESS AND DATA LONG (ADL) mode. Selection of the memory mode is controlled by the ADL mode bit.

The multiple memory modes of the processor allow CPU products to easily mix existing Z80 code or Z180 code with new ADL mode code. Collectively, the Z80 and ADL memory modes may be referred to as ADL modes, because they are controlled by the ADL bit.

Z80 MEMORY Mode

When the ADL bit is cleared to 0, the CPU operates using Z80-compati- ble addressing and Z80-style 16-bit CPU registers. This Z80 MEMORY mode is also occasionally referred to as non-ADL mode. Z80 MEMORY mode is the default operating mode on reset.

In Z80 MEMORY mode (or its alternate term, Z80 mode), all of the multibyte internal CPU registers are 16 bits. Also, the 16-bit Stack Pointer Short (SPS) register is used to store the stack pointer value.

Additionally, the CPU employs an 8-bit MBASE address register that is always prepended to the 16-bit Z80 mode address. The complete 24-bit address is returned by {MBASE, ADDR[15:0]}. The MBASE address register allows Z80 code to be placed anywhere within the available

16MB addressing space. This placement allows for 256 unique Z80 code blocks within the 16MB address space, as illustrated in Figure 2.

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When MBASE is set to 00h, the CPU operates like a classic Z80 with 16bit addressing from 0000h to 00FFh. When MBASE is set to a nonzero value, the 16-bit Z80-style addresses are offset to a new page, as defined by MBASE.

By altering MBASE, multiple Z80 tasks can possess their own individual Z80 partitions. The MBASE register can only be changed while in ADL mode, thereby preventing accidental page switching when operating in Z80 MEMORY mode. The MBASE address register does not affect the

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length of the CPU register. In Z80 mode, the CPU registers remain 16 bits, independent of the value of MBASE. For more information on the CPU registers in Z80 mode, refer to the eZ80® CPU Registers in Z80 Mode section on page 14.

ADL MEMORY Mode

Setting the ADL bit to 1 selects ADL mode. This memory mode is referred to as ADL MEMORY mode or ADL mode. In ADL mode, the user application can take advantage of the CPU’s 16MB linear addressing space, 24-bit CPU registers, and enhanced instruction set. When ADL mode is selected, MBASE does not affect memory addressing. The ADL mode memory map is illustrated in Figure 3.

Note: There are no pages in ADL mode.

ADL Mode

16 MB Linear

Memory Space

Figure 3. ADL Addressing Mode Memory Map

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In ADL mode, the CPU’s multibyte registers are expanded from 16 to 24 bits. A 24-bit Stack Pointer Long (SPL) register replaces the 16-bit Stack Pointer Short (SPS) register. For more information on the CPU registers in ADL mode, refer to the eZ80® CPU Registers in ADL Mode section on page 16.

In ADL mode, all addresses and data are 24 bits. All data READ and WRITE operations pass 3 bytes of data to and from the CPU when operating in ADL mode (as opposed to only 2 bytes of data while in Z80 mode operation). Thus, instructions operating in ADL mode may require more clock cycles to complete than in Z80 mode. Although MBASE does not affect operation during ADL mode, the MBASE register can only be written to when operating in ADL mode.