Index

Numerics

16-MB address mode 1

16-MB linear addressing 1, 9

24-bit linear addressing 2, 7, 13, 49

24-bit registers 2, 16

64-KB address mode 1

8-bit data path 2

A

About This Manual xi accumulator register 11 ADC A, (HL) 107 ADC A, (IX/Y + d) 109 ADC A, ir 108

ADC A, n 110 ADC A, r 111 ADC HL, rr 113 ADC HL, SP 115 ADD A, (HL) 116

ADD A, (IX/Y + d) 118 ADD A, ir 117

ADD A, n 119 ADD A, r 120 ADD HL, rr 122 ADD HL, SP 124 ADD IX/Y, rxy 125 ADD IX/Y, SP 127

ADD with Carry 107–111, 113, 115 ADD without Carry 116–120, 122, 124–

125, 127

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Add/Subtract Flag 20, 452

ADDRESS AND DATA LONG mode 2– 3, 7–10, 12–13, 16, 24–25, 28, 34, 36– 37, 41, 43–47, 49–51, 53–55, 61, 64, 89, 97–98

and Z80 mode 24 applications 55, 58

bit 7, 9, 27, 35, 37–39, 42–43, 49–50, 53–55

bit, Interrupt Mode 0 Operation 52 bit, Interrupt Mode 1 Operation 54 bit, mixed 13, 461

bit, Nonmaskable Interrupt Operation 50

code 25 Address Generator 4 address translation 4

ADL mode—see ADDRESS AND DATA LONG mode

ADL MEMORY Mode—see ADDRESS AND DATA LONG mode

All Uppercase Letters, Use of xv Alternate Register Set 11, 15–16 ALU—see Arithmetic Logic Unit AND A, (HL) 128

AND A, (IX/Y + d) 130 AND A, ir 129

AND A, n 131 AND A, r 132

Arithmetic Logic Unit 2, 4 assembly code xi

Assembly Language Source Program

Example 70

Assembly of the Op Code Suffixes 33

B

backward compatibility 7 Bit b, (HL) 134

Bit b, (IX/Y + d) 136 Bit b, r 138

Bit Numbering xv Bit Test 134, 136, 138 Braces xiv

Brackets xiii

C

CALL cc, Mmn 140 CALL instruction 5, 46 CALL Mmn 143 CALL Subroutine 143 Carry Flag 19, 455

CCF—see Complement Carry Flag Compare and Decrement 153

with Repeat 154 Compare and Increment 156

with Repeat 157

Compare with Accumulator 147–151 compatibility, backward 7 Complement Accumulator 159 Complement Carry Flag 61–62, 64, 146 Conditional CALL Subroutine 140 Conditional Jump 221

Relative 229

Conditional Return from Subroutine 353 control block 2, 4, 25, 28, 453

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control block, mode 3–4 control transfer events 3, 5 control transfer instruction 34 Courier Typeface xiii

CP A, (HL) 147

CP A, (IX/Y + d) 149 CP A, ir 148

CP A, n 150 CP A, r 151

CPD—see Compare and Decrement CPDR—see Compare and Decrement with

Repeat

CPI—see Compare and Increment CPIR—see Compare and Increment with

Repeat

CPL—see Complement Accumulator CPU control block 4

CPU Instruction Set 69 CPU Registers 4

Customer Feedback Form 474 cycle time 4

D

DAA—see Decimal Adjust Accumulator data block 2, 4, 25, 28

data bus 4, 51–53, 55, 58, 180 memory and I/O space 63

Data Selector 4 DEC—see Decrement DEC (HL) 163

DEC (IX/Y + d) 166 DEC ir 164

DEC IX/Y 165 DEC r 167

DEC rr 169 DEC SP 170

Decimal Adjust Accumulator 160 Decrement 163–167, 169–170 Decrement B Jump Not Zero 172 DI—see Disable Interrupt Disable Interrupt 14, 48, 171, 460

DJNZ—see Decrement B Jump Not Zero

E

EI—see Enable Interrupt

Enable Interrupt 14, 48–49, 76, 82, 173, 356, 460

Op Code Map 445

ending program counter 35, 37–44, 50–55, 140–141, 143–144, 221, 223, 225, 227, 350–351, 353–354, 356–357, 359–360, 392–393

EX (SP), HL 176

EX (SP), IX/Y 177 EX AF, AF’ 174 EX DE, HL 175

Exchange AF and AF’ 174 Exchange DE with HL 175 Exchange Stack and HL Register 176

Exchange Stack and Index Register 177 Exchange Working Register Set with

Alternate Register Set 178 EXX instruction 64, 73, 178

eZ80 xvi, 1, 2, 27, 28, 45, 48–49, 51, 64 eZ80 CPU Response to a Maskable

Interrupt 51

eZ80 CPU Response to a Nonmaskable Interrupt 49

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eZ80 MEMORY mode prefix bytes 34 eZ80 memory READ and WRITE

operations 2, 4, 7–9, 11, 13, 18–19, 22, 24–26, 28–29, 32–34, 38

F

full 24-bit address mode 1

H

Half-Carry Flag 21, 458

HALT mode 3, 179

Hexadecimal Values xiii

I

IEF1 bit flag 14–18, 48, 81–82, 99, 171, 173, 359, 458

IEF2 14–18, 21, 48, 50–55, 78, 88, 99, 171, 173, 231, 235, 237, 359, 458

IEF2, purpose of 49

IEF2, temporary storage location 48 IM 0 51

Op Code Map 448 IM 1 51, 53

Op Code Map 448 IM 2 51

Op Code Map 448 IM n 180

IN A, (n) 182

IN—see Input from I/O IN r, (BC) 183

IN0 r, (n) 185 INC (HL) 187

INC (IX/Y + d) 190 INC—see Increment

Relative 230

Relative Conditional 229

Jump not 0 instruction, Decrement B 172

L

Last In, First Out 13 LD—see Load instruction LD (HL), IX/Y 237, 238 LD (HL), n 239

LD (HL), r 240 LD (HL), rr 241

LD (IX/Y + d), IX/Y 252 LD (IX/Y + d), n 253 LD (IX/Y + d), r 254 LD (IX/Y + d), rr 256 LD (Mmn), A 259

LD (Mmn), IX/Y 260 LD (Mmn), rr 261 LD (Mmn), SP 263 LD (rr), A 279

LD A, (IX/Y + d) 232 LD A, (Mmn) 234 LD A, (rr) 236

LD A, I 231, 237

LD A, MB 233

LD A, R 235

LD HL, Mmn in ADL Mode 28 LD HL, Mmn in Z80 Mode 27 LD I, A 243

LD ir, ir’ 244 LD ir, n 245 LD ir, r 246

LD IX/Y, (HL) 248

LD IX/Y, (IX/Y + d) 249

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LD IX/Y, (Mmn) 251

LD IX/Y, Mmn 250 LD MB, A 258

LD r, (HL) 265

LD r, (IX/Y + d) 268 LD R, A 264

LD r, ir 266 LD r, n 270 LD r, r’ 271

LD rr, (HL) 273

LD rr, (IX/Y + d) 274 LD rr, (Mmn) 277 LD rr, Mmn 276

LD SP, (Mmn) 283 LD SP, HL 280 LD SP, IX/Y 281 LD SP, Mmn 282

LDD—see Load and Decrement LDDR—see Load and Decrement with

Repeat

LDI—see Load and Increment LDIR—see Load and Increment with

Repeat

LEA—see Load Effective Address LEA IX/Y, IX+d 290

LEA IX/Y, IY+d 291 LEA rr, IX+d 292 LEA rr, IY+d 293 legacy code 46, 47

LIFO—see Last In, First Out linear addressing, 16MB 1, 9

24-bit 2, 7, 13, 49

Load instruction 5, 70, 244–246

Load Accumulator 231, 232, 233, 234, 235, 236, 237

Load and Decrement 284 with Repeat 285

Load and Increment 287 with Repeat 288

Load Effective Address 290, 291, 292, 293 Load Index Register 248–251

Load Indirect 238–241, 259–261, 263, 279 with Offset 252–254, 256

Load Interrupt Vector 242, 243 Load MBASE 258

Load Refresh Counter 264

Load Register 265–266, 268, 270–271, 273–274, 276–277

Load Stack Pointer 280–283 Logical AND 128–132

Logical Exclusive OR 438–440, 442–443 Logical OR 298–302

LSB and MSB, Use of the Terms xiv

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Guidelines 46

Mixed-ADL Bit 13, 461

bit flag 18, 102, 104, 391, 426 control bit 45–46, 350, 353, 356–357,

359–360 single-bit flag 15–17

MLT rr 294 MLT SP 295 Mode Control 3

Multiply Register 294 Multiply Stack Pointer 295

N

NEG—see Negate Accumulator Negate Accumulator 296 NMI—see nonmaskable interrupt No Operation 297

nonmaskable interrupt 48–50, 76, 359, 464 Return from 359

NOP—see No Operation

M

MADL—see Mixed-ADL Bit

Main Register Set 11, 15–16 Manual Conventions xiii Manual Objectives xi Manual Organization xi maskable interrupt 48, 51

mode 51

MBASE address register 4, 7–8, 12–14, 64 Load MBASE instruction 258

memory addressing modes 64 MIXED MEMORY mode 61

applications 55, 58

O

Op Code Decoder 4 Op Code maps 445

Op Code Suffixes for Memory Mode Control 24

Op Codes, instruction fetch of 3 operands, instruction fetch of 3 OR A, (HL) 298

OR A, (IX/Y + d) 300 OR A, ir 299

OR A, n 301 OR A, r 302

PUSH mnemonic 339, 341, 343 PUSH rr 342

Push Stack 338, 340, 342

PUSH, Op Code Map 445, 447, 449

R

real-time operating system 1 Register Access Abbreviations xv register bank contents, exchanging 11 registers, special purpose 4

Related Documents xiii RES b, (HL) 344

RES b, (IX/Y+d) 346 RES b, r 348

Reset Bit 344, 346, 348

Reset MIXED MEMORY Mode Flag 391 Restart instruction 5, 45, 64, 392 RET—see Return instruction

RET cc 353

RETI—see Return from Maskable Interrupt

RETI.L 46

RETN—see Return from Nonmaskable Interrupt

RETN.L 46

Return from Maskable Interrupt 356 Return from Nonmaskable Interrupt 359 Return from Subroutine 350

Return Information 474 Return instruction 5, 350

Risks with Using the .SIL Suffix 29 RL—see Rotate Left

RL (HL) 362

RL (IX/Y+d) 363

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RL r 365

RLA—see Rotate Left Accumulator RLC—see Rotate Left with Carry RLC (HL) 368

RLC (IX/Y+d) 369 RLC r 371

RLCA—see Rotate Left with Carry– Accumulator

RLD—see Rotate Left Decimal Rotate Left 362–363, 365 Rotate Left Accumulator 367 Rotate Left Decimal 374

Rotate Left with Carry 368, 369, 371 Rotate Left with Carry–Accumulator 373 Rotate Right 376, 378, 380

Rotate Right Decimal 389

Rotate Right with Carry 383, 384, 386 Rotate Right with Carry–Accumulator 388 Rotate Right–Accumulator 382

RR—see Rotate Right RR (HL) 376

RR (IX/Y+d) 378 RR r 380

RRA—see Rotate Right Accumulator RRC—see Rotate Right with Carry RRC (HL) 383

RRC (IX/Y+d) 384 RRC r 386

RRCA—see Rotate Right with Carry– Accumulator

RRD—see Rotate Right Decimal RSMIX instruction 46, 391 RST—see Restart instruction RST n 392

S

Safeguards xvi

SBC—see Subtract with Carry SBC A, (HL) 395

SBC A, (IX/Y+d) 397 SBC A, ir 396

SBC A, n 398 SBC A, r 399 SBC HL, rr 401 SBC HL, SP 403 SCF 404

Set and Clear, Use of the Words xiv SET b, (HL) 405

SET b, (IX/Y+d) 406 SET b, r 408

Set Bit 405, 406, 408

Set Carry Flag 404

Set Interrupt Mode 180

Set MIXED MEMORY Mode Flag 46, 49, 426

Shift Left Arithmetic 410, 411, 413 Shift Right Arithmetic 416, 417, 419 Shift Right Logical 421, 422, 424 Sign Flag 22, 465

Single-cycle fetch 2

Single-Instruction Memory Mode Changes 26

single-instruction mode 24 SLA (HL) 410

SLA (IX/Y+d) 411 SLA r 413

SLEEP mode 3, 415 SLP—see SLEEP mode software module 1

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special purpose registers 4

SPL—see Stack Pointer Long register SPS—see Stack Pointer Short register SRA (HL) 416

SRA (IX/Y+d) 417 SRA r 419

SRL (HL) 421 SRL (IX/Y+d) 422 SRL r 424

Stack Pointer 64

Stack Pointer Long register 12, 64, 72, 263, 280–283, 295, 403

stack 46

Stack Pointer Short register 7, 10, 13, 14, 64, 72, 263, 280–283, 295, 403

starting program counter 35–44, 50–55 state machine 3

STMIX—see Set MIXED MEMORY Mode Flag

SUB—see Subtract without Carry SUB A, (HL) 427

SUB A, (IX/Y+d) 429 SUB A, ir 428

SUB A, n 430 SUB A, r 431

Subtract with Carry 395–399, 401, 403 Subtract without Carry 427–431

Suffix Completion by the Assembler 32 Suffix Example 1 27

Suffix Example 2 28

Suffix Example 3 29 Suffix Example 4

LD (HL), BC in Z80 Mode 30

T

Test 433–435

Test I/O Byte 437

Trademarks xvi

TST—see Test

TST A, (HL) 433

TST A, n 434

TST A, r 435

TSTIO instruction 63

TSTIO n 437

W

Working Registers 11, 15, 16, 17 general purpose 64

X

XOR A, (HL) 438

XOR A, (IX/Y+d) 440

XOR A, ir 439

XOR A, n 442

Z

Z180 xvi, 1, 2

Z180 code 7

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Z180 Instruction 34

Z80 xvi, 1, 44, 53, 295, 338

Z80 code blocks 7

Z80 legacy programs 7

Z80 MEMORY mode 7, 13

Z80 Memory Mode Base Address Register

12

Z80 Memory Mode Map 8

Z80 memory page 13

Z80 mode xii, 2, 7, 9, 12–14, 16, 24–25, 27, 29, 34–35, 37–47, 50, 52–54, 61, 64, 97– 98, 115, 124, 127, 141, 144, 170, 176– 177, 189, 193–194, 221, 223, 225, 227, 233, 263, 280–283, 295, 328, 330, 332, 334, 336, 338, 340, 342, 351, 354, 357, 360, 393, 403

code 25, 55, 58 operation 4

Z80 processor core 2

Z80-compatible addressing 7

Z80-compatible mode 1

Z80-style address 13

Z80-style registers 7 Zero Flag 22, 467